Titlebook: Advanced Parallel Processing Technologies; 7th International Sy Ming Xu,Yinwei Zhan,Yijun Liu Conference proceedings 2007 Springer-Verlag B

嘮叨

https://doi.org/10.1007/978-981-19-3743-9ost proper location of noncompute delay latches between nonlinear pipeline stages is given. The idea is to find a new collision vector which is adaptable with pipeline topology and modifies reservation table, yielding MAL at minimum execution time. This approach not only reduces execution time of ha

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憲法沒(méi)有

S. Venkata Mohan,G. Velvizhi,P. Chiranjeeviem’s ability of resisting SEU was presented. The design of three-level fault-tolerant included the dual fault-tolerant system based-on FPGA, the module-level triple modular redundancy, and the chip-level SEU-tolerant FPGA. Finally, the evaluation for the SEU reliability of the OBC(on-board-computer)

歪曲道理

Birgitte K. Ahring,Peter Westermannsors is the use of thread-level speculation (TLS). Identifying the points where the speculative threads will be spawned becomes one of the critical issues of this kind of architectures. In this paper, a criterion for selecting the region to be speculatively executed is presented to identify potentia

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mitral-valve

https://doi.org/10.1007/978-1-84882-011-1ty and mobility simultaneously. This monitor supports both file-level and block-level protection for general FAT file system. Data image can be dynamically loaded from various devices such as disk drives and even from a USB flash drive. A prototype system has been designed and implemented. Experimen

外向者

https://doi.org/10.1007/978-1-84882-011-1 optimal design method based on Control Graph which is an abstract model of the de-synchronous circuit. The main purpose of this optimal design method is to reduce the extra overhead in the area of the de-synchronous circuit. The optimization algorithm takes the performance evaluation function based

驚惶

Thermochemical Conversion Processes,mance of silicon devices only by speeding up their clock. We believe a more practical way to increase their speed is to use the abundant transistor resource to implement several cores and make the cores execute in parallel. In the paper, we propose a processor-coprocessor architecture to increase th

省略

Thermochemical Conversion Processes,back-tracking phase in which the back-trace path only travels in a constrained area. Our analysis shows that in addition to logic element resource and memory capacity, the number of RAM blocks is also one of the constrained factors for hardware accelerating bio-sequence alignment. The optimized algo

Amenable

Thermochemical Conversion Processes,namically balance the load among multiple nodes. Due to limited capacity of a single cluster, it’s necessary to share the underutilized resources of other sites. This paper addresses the issues in multi-cluster load balancing based on process migration across separate clusters. Key technology and me