| 書目名稱 | Wafer Level 3-D ICs Process Technology | | 編輯 | Chuan Seng Tan,Ronald J. Gutmann,L. Rafael Reif | | 視頻video | http://file.papertrans.cn/1021/1020138/1020138.mp4 | | 概述 | Focuses on the foundry-based process technology for the fabrication of 3-D ICs.Discusses the technology platform for pre-packaging wafer level 3-D ICs.Includes chapters contributed by various experts | | 叢書名稱 | Integrated Circuits and Systems | | 圖書封面 |  | | 描述 | Three-dimensional (3D) integration is clearly the simplest answer to most of the semiconductor industry’s vexing problems: heterogeneous integration and red- tions of power, form factor, delay, and even cost. Conceptually the power, latency, and form factor of a system with a ?xed number of transistors all scale roughly linearly with the diameter of the smallest sphere enclosing frequently interacting devices. This clearly provides the fundamental motivation behind 3D technologies which vertically stack several strata of device and interconnect layers with high vertical interconnectivity. In addition, the ability to vertically stack strata with - vergent and even incompatible process ?ows provides for low cost and low parasitic integration of diverse technologies such as sensors, energy scavengers, nonvolatile memory, dense memory, fast memory, processors, and RF layers. These capabilities coupled with today’s trends of increasing levels of integrated functionality, lower power, smaller form factor, increasingly divergent process ?ows, and functional diversi?cation would seem to make 3D technologies a natural choice for most of the semiconductor industry. Since the concept of verti | | 出版日期 | Book 2008 | | 關鍵詞 | Applications enabled by 3-D integration; CMOS; Diffusion; Technologie; Three-dimensional (3-D) integrati | | 版次 | 1 | | doi | https://doi.org/10.1007/978-0-387-76534-1 | | isbn_softcover | 978-1-4419-4562-4 | | isbn_ebook | 978-0-387-76534-1Series ISSN 1558-9412 Series E-ISSN 1558-9420 | | issn_series | 1558-9412 | | copyright | Springer-Verlag US 2008 |
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