標題: Titlebook: VLSI-SoC: From Systems to Silicon; IFIP TC10/ WG 10.5 T Ricardo Reis,Adam Osseiran,Hans-Joerg Pfleiderer Conference proceedings 2007 IFIP I [打印本頁] 作者: Reagan 時間: 2025-3-21 20:09
書目名稱VLSI-SoC: From Systems to Silicon影響因子(影響力)
書目名稱VLSI-SoC: From Systems to Silicon影響因子(影響力)學科排名
書目名稱VLSI-SoC: From Systems to Silicon網絡公開度
書目名稱VLSI-SoC: From Systems to Silicon網絡公開度學科排名
書目名稱VLSI-SoC: From Systems to Silicon被引頻次
書目名稱VLSI-SoC: From Systems to Silicon被引頻次學科排名
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書目名稱VLSI-SoC: From Systems to Silicon年度引用學科排名
書目名稱VLSI-SoC: From Systems to Silicon讀者反饋
書目名稱VLSI-SoC: From Systems to Silicon讀者反饋學科排名
作者: LAST 時間: 2025-3-21 22:12
Milos Stanisavljevic,Alexandre Schmid,Yusuf Leblebici a close relationship between avoidable vertices in a graph and its minimal triangulations and identify new algorithmic uses of avoidable vertices. More specifically, applying Lexicographic Breadth First Search and bisimplicial elimination orderings, we derive a polynomial-time algorithm for the max作者: Excitotoxin 時間: 2025-3-22 00:25
N. Badereddine,P. Girard,S. Pravossoudovitch,A. Virazel,C. Landrault two fundamental graph operations: clique-sum and subdivisions. In both cases, we provide a lower and an upper bound of the possible amount of changes and provide (almost) tight examples. Finally, we prove that the decision version of the problem of finding .(.) is NP-complete even for the family of作者: MONY 時間: 2025-3-22 05:47 作者: patriot 時間: 2025-3-22 10:19
Defragmentation Algorithms for Partially Reconfigurable Hardware, We present defragmentation algorithms that minimize different types of costs. With the help of a detailed simulation model and a benchmark, we finally provide realistic simulation results and compare the different algorithms.作者: arsenal 時間: 2025-3-22 13:14 作者: 顛簸下上 時間: 2025-3-22 17:38
A Traffic Injection Methodology with Support for System-Level Synchronization,ogy to split such applications in execution subflows and to adjust the overall execution stream based upon hardware events; a reactive simulation device capable of correctly replicating such software behaviours in the MPSoC design phase. Additionally, we validate the proposed concept by showing cycl作者: deceive 時間: 2025-3-23 00:05
Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs,tion model was implemented inside a framework that enables the description of different applications and NoC topologies. Comparing the resulting mappings, the model proposed displays an average improvement of 45% in energy saving.作者: 出血 時間: 2025-3-23 01:28
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Coest quality metric, and schedules the transportation of the selected test data volume on the Test Access Mechanism such that the system’s test quality is maximized and the test data fits the ATE’s memory. We have implemented the proposed technique and the experimental results, produced at reasonable作者: 變化無常 時間: 2025-3-23 08:43
Conference proceedings 2007est of these systems. VLSI-SOC conferences aim to address these exciting new issues. The 2005 edition of VLSI-SoC maintained the traditional structure, which has been successful at the previous VLSI-SOC conferences. The quality of submissions (107 papers from 26 countries) made the selection process作者: genuine 時間: 2025-3-23 13:47 作者: 混合,攙雜 時間: 2025-3-23 15:37
oach, we describe an interactive proof system for accepting any language in .after a logspace reduction, where the verifier is logspace-bounded and the protocol requires polylog time. These results are proved by describing .computations as computations over arithmetic circuits using . and . gates, a作者: Erythropoietin 時間: 2025-3-23 20:57 作者: 政府 時間: 2025-3-24 02:08 作者: prostatitis 時間: 2025-3-24 03:37 作者: 法律的瑕疵 時間: 2025-3-24 10:00 作者: Incorruptible 時間: 2025-3-24 11:44
Bertrand Folco,Vivian Brégier,Laurent Fesquet,Marc Renaudiny-as-you-go model, commonly used for utilities (electricity and water). We model such a system as a capacitated graph, and study a basic allocation problem: given a set of jobs, each demanding computing and bandwidth resources and yielding a profit, determine which feasible subset of jobs yields the作者: 叫喊 時間: 2025-3-24 16:20
Chul Kim,Alex Rassau,Stefan Lachowicz,Saeid Nooshabadi,Kamran Eshraghians users. For instance, in QoS multicasting, a source needs to efficiently transmit a message to a set of receivers, each requiring support at a different QoS level (e.g., bandwidth). This can be formulated as the . problem: Here, each link of the underlying network is associated with a priority valu作者: Stable-Angina 時間: 2025-3-24 20:45
Alberto Donato,Fabrizio Ferrandi,Massimo Redaelli,Marco Domenico Santambrogio,Donatella Sciutoum-length matching on all points. We say that . is .-. if for any subset . of . edges of . it holds that . is a maximum-length matching on points .. We show that local maximum matchings are good approximations of global ones..Let . be the infimum ratio of the length of any .-local maximum matching t作者: 赤字 時間: 2025-3-25 02:02
Milos Stanisavljevic,Alexandre Schmid,Yusuf Leblebicion the existence of simplicial vertices in chordal graphs, Ohtsuki et al.?proved in 1976 that every graph has an avoidable vertex. In a different generalization, Chvátal et al.?gave in 2002 a characterization of graphs without long induced cycles based on the concept of simplicial paths. We introduc作者: AIL 時間: 2025-3-25 04:29 作者: 酷熱 時間: 2025-3-25 09:23 作者: 愚笨 時間: 2025-3-25 12:40 作者: Wernickes-area 時間: 2025-3-25 19:40
César A. M. Marcon,José C. S. Palma,Ney L. V. Calazans,Fernando G. Moraes,Altamiro A. Susin,Ricardo here separators of size .=O(n.) for a set of points in R...We present randomized, dynamic algorithms to maintain separators and answer queries about a dynamically changing point set. Our algorithms maintain a separator in expected time .(log .) and maintain a separator tree in expected time .(log..)作者: debouch 時間: 2025-3-25 22:51 作者: FEAT 時間: 2025-3-26 01:03
Erik Larsson,Stina Edbomts . is defined as . if . and it is zero if .. Here, .(.,?.) is the (geodesic) Euclidean distance between . and .. For a real number ., a graph .(.,?.) is called a . for the weighted set . of points if for any two points . and . in . the distance between . and . in graph . is at most ... for a real 作者: TATE 時間: 2025-3-26 07:49
Achraf Dhayni,Salvador Mir,Libor Rufer,Ahcène Bounceure (.,?.)-geodesic. Given a set ., let .. If ., we call . a convex set. The convex hull, denoted by ., is the smallest convex set containing .. A subset . of vertices of a graph . is a hull set if .. Moreover, . is a geodetic if .. The hull number .(.) of a graph . is the minimum size of a hull set. 作者: Tincture 時間: 2025-3-26 08:35
N. Badereddine,P. Girard,S. Pravossoudovitch,A. Virazel,C. Landraultpath of ., for some .. The monitoring edge-geodetic number of ., denoted by .(.), is the minimum cardinality of such an MEG-set. This notion provides a graph theoretic model of the network monitoring problem..In this article, we compare .(.) with some other graph theoretic parameters stemming from t作者: Cardiac 時間: 2025-3-26 14:13
Thilo Pionteck,Thomas Stiefmeier,Thorsten Staake,Manfred Glesner deduce some results proved in (Saeid et al. Rocky Mountain J. Math. 48(3) (2018), 729–751) and (Nilesh et al. arXiv (2022), arXiv:2205.04916). We also characterize rings, posets and reduced semigroups whose zero-divisor graphs and ideal based zero-divisor graphs are perfect. As a consequence, we ch作者: Bone-Scan 時間: 2025-3-26 18:01 作者: disparage 時間: 2025-3-26 22:14
ing encodings of inputs, using the polylogarithmically checkable codes introduced in the context of transparent proofs..We also characterize .and .via public-coin interactive proof systems where the verifier is logspace-bounded, but has restricted access to auxiliary storage.作者: Invertebrate 時間: 2025-3-27 01:12
Erik Larsson,Stina Edbome points in . belonging to either . or located in the given simple polygon. Note that .(.,?.) is the geodesic Euclidean distance between . and . in the case of simple polygons whereas in the case of . it is the Euclidean distance along the line segment joining . and ..作者: conference 時間: 2025-3-27 05:59 作者: 簡略 時間: 2025-3-27 10:01
Pareto Points in SRAM Design Using the Sleepy Stack Approach, more than 2.77X leakage power reduction at a cost of 16% delay increase and 113% area increase. Alternatively, by widening wordline transistors and transistors in the pull-down network, the sleepy stack SRAM cell can achieve 2.26X leakage reduction without increasing delay at a cost of a 125% area penalty.作者: 思想 時間: 2025-3-27 15:42 作者: Hemiplegia 時間: 2025-3-27 17:56
Shankar Mahadevan,Federico Angiolini,Jens Spars?,Luca Benini,Jan Madsenhe procedure terminates. We show how to add one set to . in . amortized time plus the time needed to find all sets of . intersecting the newly added set, where . is the cardinality of ., . is the number of sets in . intersecting the newly added set, and . is the inverse of the Ackermann function.作者: 誘使 時間: 2025-3-27 22:27 作者: cipher 時間: 2025-3-28 04:10
Fraidy Bouesse,Marc Renaudin,Gilles Sicardhe Minimum-Area Tour (.) problem. The first problem is a variant of the power assignment problem in radio networks, the second problem is a related natural problem, and the third problem is a variant of the traveling salesman problem.作者: 瘋狂 時間: 2025-3-28 09:55
Alberto Donato,Fabrizio Ferrandi,Massimo Redaelli,Marco Domenico Santambrogio,Donatella Sciutoproved bounds for .: . and .. We also show that every pairwise crossing matching is unique and it is globally maximum..Towards our proof of the lower bound for . we show the following result which is of independent interest: If we increase the radii of pairwise intersecting disks by factor ., then the resulting disks have a common intersection.作者: 幻影 時間: 2025-3-28 13:31 作者: 群居動物 時間: 2025-3-28 17:56
César A. M. Marcon,José C. S. Palma,Ney L. V. Calazans,Fernando G. Moraes,Altamiro A. Susin,Ricardo .-neighborhood graphs..We also give a general technique for transforming a class of expected time randomized incremental algorithms that use random sampling into incremental algorithms with high likelihood time bounds. In particular, we show how we can maintain separators in time .(log..) with high likelihood.作者: DUST 時間: 2025-3-28 21:41 作者: 入會 時間: 2025-3-29 02:50
Achraf Dhayni,Salvador Mir,Libor Rufer,Ahcène Bounceurdding a new vertex . for each vertex . of . and joining . to the neighbors of . in .. In this paper, we study the geodetic and hull numbers of shadow graphs. Bounds for the geodetic and hull numbers of shadow graphs are obtained and for several classes exact values are determined. Graphs . for which . are characterized.作者: Gene408 時間: 2025-3-29 03:24
Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems o In order to meet the software requirements of complex systems, the solution is provided with a porting of a real–time gnu/Linux os, μCLinux, which allows software processes to exploit a rich set of features, and with a Linux module that simplifies and enhances the handling of reconfiguration.作者: 護身符 時間: 2025-3-29 09:33 作者: thyroid-hormone 時間: 2025-3-29 13:18
Paul Franzon,David Nackashi,Christian Amsinck,Neil DiSpigna,Sachin Sonkusaledel, where each robot is equipped with an externally visible light that can assume colors from a fixed set of colors, using 9 colors and .(.) rounds. In this work, we present an algorithm that requires only 2 colors and .(.) rounds. The number of colors is optimal since at least two colors are required for point robots?[.].作者: 輕快帶來危險 時間: 2025-3-29 18:30
Markus Koester,Heiko Kalte,Mario Porrmann,Ulrich Rückertn that done by the best possible sequential one; and (iii) a model of computation is introduced which is an extension of the strongest variant of the PRAM, yet it requires no more resources than its weakest variant.作者: Barrister 時間: 2025-3-29 20:10 作者: Little 時間: 2025-3-30 00:17 作者: commensurate 時間: 2025-3-30 04:12 作者: 泄露 時間: 2025-3-30 08:29
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits,-input gates. Optimization is achieved by applying a technology mapping algorithm with a library of asynchronous standard cells called TAL. This work is a part of the back-end of our synthesis flow from high level language. Throughout the paper, a digit-slice radix 4 ALU is used as an example to illustrate the methodology and show the results.作者: 公豬 時間: 2025-3-30 13:05 作者: BULLY 時間: 2025-3-30 18:35
A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Funcrealistic constraints. A structured fault modeling architecture is also proposed, which is together with the tool a part of the new design method where reliability is considered as a central focus from an early development stage.作者: follicle 時間: 2025-3-30 22:47
Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping,LS systems. A demonstrative platform is implemented onto an Altera Stratix FPGA. It includes synchronous standard IP cores and asynchronous modules connected through an asynchronous 6x6 crossbar. Results about communication costs across the Asynchronous NoC and synchronous/asynchronous interfaces are reported.作者: Concomitant 時間: 2025-3-31 03:23 作者: 認識 時間: 2025-3-31 05:43 作者: SLUMP 時間: 2025-3-31 09:29
Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgt Differential Power Analysis Attacks. This countermeasure exploits the properties of the QDI circuit acknowledgement signals to introduce temporal variations so as to randomly desynchronize the data processing times. The efficiency of the countermeasure, in terms of DPA resistance, is formally pres作者: 慢慢啃 時間: 2025-3-31 15:28
A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multipli modified to handle the sign bits in 2’s complement and uses a radix-4 encoding to reduce the partial product lines. The second architecture implemented was the widely used Modified Booth multiplier. We describe a design methodology to physically implement these architectures in a pipelined and non-作者: 桶去微染 時間: 2025-3-31 20:40 作者: Hay-Fever 時間: 2025-4-1 01:20
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits,its offer high robustness but do not perform well to automatically synthesize and optimize. This paper presents a new methodology to model and synthesize data path QDI circuits. The model used to represent circuits is based on Multi-valued Decision Diagrams and allows obtaining QDI circuits with two作者: 同謀 時間: 2025-4-1 03:39 作者: bioavailability 時間: 2025-4-1 09:23
Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems o of partial dynamic reconfiguration provided by the modern boards. In the resulting system, which includes a set of fixed components (such as a processor and a controller) as well as some reconfigurable area (which can be allotted to different tasks running concurrently and replaced independently of
