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標題: Titlebook: VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design; 20th IFIP WG 10.5/IE Andreas Burg,Ay?e Co?kun,Ricardo Reis Conference proc [打印本頁]

作者: Capricious    時間: 2025-3-21 16:31
書目名稱VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design影響因子(影響力)




書目名稱VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design影響因子(影響力)學科排名




書目名稱VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design網(wǎng)絡公開度




書目名稱VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design網(wǎng)絡公開度學科排名




書目名稱VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design被引頻次




書目名稱VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design被引頻次學科排名




書目名稱VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design年度引用




書目名稱VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design年度引用學科排名




書目名稱VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design讀者反饋




書目名稱VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design讀者反饋學科排名





作者: VICT    時間: 2025-3-21 22:14

作者: Enthralling    時間: 2025-3-22 02:20
Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnectionsthe number of faulty interconnections. Results for MPEG4 and VOPD applications running on the NoC with different faulty case-study scenarios show that the proposed techniques can tolerate many faulty interconnections with a low area, performance and power overheads.
作者: 運動性    時間: 2025-3-22 05:40

作者: 內閣    時間: 2025-3-22 10:22
Jeremy Constantin,Ahmed Dogan,Oskar Andersson,Pascal Meinerzhagen,Joachim Rodrigues,David Atienza,Ann der Informationskette nicht nur das ihr zugeh?rige spezifische Eiwei? gebildet wird, sondern da? sie veranla?t, da? auch die ., Eiwei?e und andere chemische K?rper gebildet werden, die den Stoffwechsel der Zellen kennzeichnen, schon die au?erordentlich mannigfaltigen Stoffe, die für die Fermente n
作者: BLINK    時間: 2025-3-22 13:43

作者: 清楚    時間: 2025-3-22 20:17

作者: 規(guī)范要多    時間: 2025-3-22 22:12
Anelise Kologeski,Caroline Concatto,Fernanda Lima Kastensmidt,Luigi Carroxperimenten, wie sie bei der leichteren Zug?nglichkeit der Geschlechtsdrüsen für diese besonders verst?ndlich sind, l??t sich dazu wohl mit einiger Sicherheit folgendes sagen: Es ist auffallend, wie mit Sch?digungen oder Exstirpationen irgendwelcher Drüsen mit innerer Sekretion und somit auch der Ge
作者: 樹膠    時間: 2025-3-23 03:15

作者: BOON    時間: 2025-3-23 05:48

作者: Crayon    時間: 2025-3-23 11:43
Neil Di Spigna,Daniel Schinke,Srikant Jayanti,Veena Misra,Paul Franzon
作者: 消極詞匯    時間: 2025-3-23 16:45

作者: PLIC    時間: 2025-3-23 19:44
Andy Motten,Luc Claesen,Yun Pan sich dann mit der sprunghaften Entwicklung der Herz- und Lungenchirurgie die Notwendigkeit für eine verfeinerte Funktionsdiagnostik, um mit gr??erer Sicherheit kardiale und respiratorische St?rungen abzugrenzen, das Operationsrisiko bei Anwendung komplizierter Anaesthesieverfahren abzusch?tzen und
作者: Prophylaxis    時間: 2025-3-24 00:30

作者: chuckle    時間: 2025-3-24 05:47

作者: ordain    時間: 2025-3-24 08:35
Zhibin Xiao,Bevan Baasung der Elektroindustrie“ h?ufiger zum Gegenstand von Abhandlungen gemacht werden. Dass die umfassende elektrotechnische Spezialindustrie in Deutschland in diesen Schriften entweder g?nzlich vernachl?ssigt, oder nur so nebenher, als von den Grosskonzernen v?llig abh?ngig, also ohne eigenen Willen, e
作者: 減至最低    時間: 2025-3-24 11:11

作者: CHANT    時間: 2025-3-24 16:32
A Smart Memory Accelerated Computed Tomography Parallel Backprojection,cted for the physical synthesis of smart memories and evaluation of the huge design space. Our experimental results show that customizing memory for the computerized tomography (CT) parallel backprojection can achieve more than 30% area and power savings while offering significant performance improvements with marginal sacrifice of image accuracy.
作者: GEST    時間: 2025-3-24 20:35
Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure,d classifier training has been performed using an indoor dataset. The system is prototyped on an FPGA board equipped with three CMOS cameras. Special care has been taken to reduce the latency and the memory footprint.
作者: 歡樂東方    時間: 2025-3-25 00:18

作者: magnanimity    時間: 2025-3-25 06:15
1868-4238 cements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of these systems.978-3-662-52529-6978-3-642-45073-0Series ISSN 1868-4238 Series E-ISSN 1868-422X
作者: 條街道往前推    時間: 2025-3-25 10:12
Spatially-Varying Image Warping: Evaluations and VLSI Implementations,perations, and memory bandwidth requirements are considered. Further, we provide an architecture based on Gaussian filtering and an architecture with bicubic interpolation and compare corresponding VLSI implementations.
作者: aquatic    時間: 2025-3-25 14:29

作者: 領袖氣質    時間: 2025-3-25 19:29

作者: 發(fā)現(xiàn)    時間: 2025-3-25 20:35

作者: Ethics    時間: 2025-3-26 00:45

作者: 暫時中止    時間: 2025-3-26 07:33
Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure,se segmented window matching for both the center-right and center-left image pairs as their scaled down image pairs is performed. The resulting cost functions are combined which results into nine different cost curves. A multi level hierarchical classifier is used to select the most promising dispar
作者: deviate    時間: 2025-3-26 11:28
Spatially-Varying Image Warping: Evaluations and VLSI Implementations,o retargeting or stereo remapping/stereo-to-multiview conversion. In contrast to the more common global image warping, e.g., zoom or rotation, the image transformation is now a spatially-varying mapping that, in principle, enables arbitrary image transformations. A practical constraint is that trans
作者: ODIUM    時間: 2025-3-26 13:04
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing,S data compression can be done both in the analog- and digital domain, digital implementations are often used on low-power sensor nodes, where an ultra-low-power (ULP) processor carries out the algorithm on Nyquist-rate sampled data. In such systems an energy-efficient implementation of the CS compr
作者: 擺動    時間: 2025-3-26 19:52

作者: 沉默    時間: 2025-3-26 23:11

作者: 吼叫    時間: 2025-3-27 03:04
Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnectionsber of faults that may occur during the process. In this work, we propose a set of fault-tolerant techniques to cope with faulty wires in Network-on-Chip (NoC). The most appropriate technique is chosen by taking into account the number of faulty wires and their location in the NoC. The goal is to co
作者: Chagrin    時間: 2025-3-27 05:38
On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis s, and during the operational phase. However, when Very Long Instruction Word (VLIW) processors are addressed these techniques require some optimization steps in order to properly exploit the parallelism intrinsic in these architectures. In this chapter we present a new method that, starting from pr
作者: subacute    時間: 2025-3-27 12:21

作者: 時間等    時間: 2025-3-27 16:04

作者: Metastasis    時間: 2025-3-27 19:13
Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates,ncept device and confirmed through simulation. The dynamic, nonvolatile, and concurrent modes of the device are described in detail. Simulations show that the device compares favorably to conventional memory devices. Applications enabled by this unified memory device are discussed, highlighting the
作者: START    時間: 2025-3-28 01:20

作者: 孤僻    時間: 2025-3-28 05:45
SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture,to lower memory power using a dual . . in a column-based . . memory with Built-In Current Sensors (BICS). Using our method, we reduce the memory power by about 40% and increase the error immunity of the memory without the significant power overhead as in previous methods.
作者: labile    時間: 2025-3-28 07:09

作者: 證明無罪    時間: 2025-3-28 13:13
CMOS Implementation of Threshold Gates with Hysteresis,orks into one composite transistor network. The new static gates are then compared to the original ones in terms of delay, area, and energy consumption. It will be shown that the new gate style is significantly faster with negligible area and energy overhead.
作者: 有權    時間: 2025-3-28 15:01

作者: Herbivorous    時間: 2025-3-28 21:33

作者: Rustproof    時間: 2025-3-28 23:28

作者: 免費    時間: 2025-3-29 04:01

作者: creditor    時間: 2025-3-29 09:42
978-3-662-52529-6IFIP International Federation for Information Processing 2013
作者: 我怕被刺穿    時間: 2025-3-29 11:26
VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design978-3-642-45073-0Series ISSN 1868-4238 Series E-ISSN 1868-422X
作者: 針葉    時間: 2025-3-29 16:12
Andreas Burg,Ay?e Co?kun,Ricardo ReisState-of-the-art research.Up-to-date results.Unique visibility
作者: Calculus    時間: 2025-3-29 19:42

作者: 冰河期    時間: 2025-3-30 02:58

作者: 誘騙    時間: 2025-3-30 05:11





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