標(biāo)題: Titlebook: VLSI-SoC: Design for Reliability, Security, and Low Power; 23rd IFIP WG 10.5/IE Youngsoo Shin,Chi Ying Tsui,Ricardo Reis Conference proceed [打印本頁] 作者: 故障 時間: 2025-3-21 19:35
書目名稱VLSI-SoC: Design for Reliability, Security, and Low Power影響因子(影響力)
書目名稱VLSI-SoC: Design for Reliability, Security, and Low Power影響因子(影響力)學(xué)科排名
書目名稱VLSI-SoC: Design for Reliability, Security, and Low Power網(wǎng)絡(luò)公開度
書目名稱VLSI-SoC: Design for Reliability, Security, and Low Power網(wǎng)絡(luò)公開度學(xué)科排名
書目名稱VLSI-SoC: Design for Reliability, Security, and Low Power被引頻次
書目名稱VLSI-SoC: Design for Reliability, Security, and Low Power被引頻次學(xué)科排名
書目名稱VLSI-SoC: Design for Reliability, Security, and Low Power年度引用
書目名稱VLSI-SoC: Design for Reliability, Security, and Low Power年度引用學(xué)科排名
書目名稱VLSI-SoC: Design for Reliability, Security, and Low Power讀者反饋
書目名稱VLSI-SoC: Design for Reliability, Security, and Low Power讀者反饋學(xué)科排名
作者: 暴露他抗議 時間: 2025-3-21 20:47
https://doi.org/10.1007/978-3-319-46097-0chip integration; computer architecture; computer-aided design (CAD); field-programmable gate array (FP作者: Transfusion 時間: 2025-3-22 04:07
978-3-319-83440-5IFIP International Federation for Information Processing 2016作者: 眨眼 時間: 2025-3-22 05:15
VLSI-SoC: Design for Reliability, Security, and Low Power978-3-319-46097-0Series ISSN 1868-4238 Series E-ISSN 1868-422X 作者: maladorit 時間: 2025-3-22 10:43
Youngsoo Shin,Chi Ying Tsui,Ricardo ReisIncludes supplementary material: 作者: 黑豹 時間: 2025-3-22 15:02 作者: Legion 時間: 2025-3-22 20:52 作者: BLINK 時間: 2025-3-23 00:07
Raimund Ubar,Lembit Jürim?gi,Elmet Orasson,Jaan Raikes labelled by the residues 0,1, ... , n-1, of integers modulo n, and 2n links i ai + e, i → ., for i = 0,1, ... , n - 1. Many 2-regular digraphs popular as topologies for interconnecting networks are special EDLNs. For example, . 2, 0; 2, 1) is the generalized de Bruijn network [6],[9], . -2, -1; -作者: 除草劑 時間: 2025-3-23 01:51
Asim Khan,Muhammad Umar Karim Khan,Muhammad Bilal,Chong-Min Kyungen evidenced by a continuously increasing number of international and local conferences, books and papers in this area. This book is also another contribution to this burgeoning area of operations research and optimization. This volume contains the contributions of the participants of the recent NAT作者: ECG769 時間: 2025-3-23 06:31 作者: FAZE 時間: 2025-3-23 11:44
Alberto Bocca,Alessandro Sassone,Donghwa Shin,Alberto Macii,Enrico Macii,Massimo Poncinoit. In this paper, we focus on the case of trees and we consider as well the . game where the amount of protection allocated to a vertex lies between 0 and 1. We introduce the online version of both . and ., in which the number of firefighters available at each turn is revealed over time. We show th作者: 保存 時間: 2025-3-23 17:49
Anvesha Amaravati,Manan Chugh,Arijit Raychowdhurylgorithmic use has also been increasing [Cygan?et?al., 2015]. New width parameters continue to be defined, for example, mim-width in 2012, twin-width in 2020, and mixed-thinness, a generalization of thinness, in 2022..The concept of . of a graph was introduced in 2007 by Mannino, Oriolo, Ricci and C作者: 柏樹 時間: 2025-3-23 19:11
Chun-Jen Tsai,Tsung-Han Wu,Hung-Cheng Su,Cheng-Yang Chenobjective is to choose a suitable dominating set . of a graph . such that the neighbourhoods of all vertices of . have distinct intersections with .. Such a dominating and separating set . is often referred to as a . in the literature. Depending on the types of dominating and separating sets used, v作者: 糾纏 時間: 2025-3-24 00:30 作者: 原來 時間: 2025-3-24 02:27 作者: Magisterial 時間: 2025-3-24 07:24
A Hardware Accelerator for Real Time Sliding Window Based Pedestrian Detection on High Resolution Ih a negligible loss in accuracy which is 16.3x and 3.8x higher than state of the art GPU and FPGA implementations respectively. Moreover 97.14?% and 10.2?% reduction in energy consumption is observed to process one frame. Finally, features are further enhanced by removing petty gradients in histogra作者: 證實 時間: 2025-3-24 11:45
Wearable ECG SoC for Wireless Body Area Networks: Implementation with Fuzzy Decision Making Chip,otocol. The patient’s ECG data is wirelessly transmitted to a PC, using ZigBee or a mobile phone. The chip is prototyped and employed in a standard 0.35?μm CMOS process. The operating voltage of Static RAM and digital circuits and analog core circuits are 3.3?V and 1?V, respectively. The total area 作者: 隱士 時間: 2025-3-24 15:46
Delay Testing Based on Multiple Faulty Behaviors,ich rely on fault dropping with explicit representation of fault lists. So in the second part of the paper, we present an ATPG method based on implicit representations of fault lists. As faults are represented implicitly, even if numbers of simultaneous faults are large and total numbers of fault co作者: 斜 時間: 2025-3-24 21:18 作者: 貨物 時間: 2025-3-25 02:53 作者: 彩色的蠟筆 時間: 2025-3-25 04:57
Raimund Ubar,Lembit Jürim?gi,Elmet Orasson,Jaan Raiko starting from a node using both types of links do not usually terminate at the same node) and the fact that they are not necessarily Cayley graphs [5]. Our ultimate goal is to investigate various properties of EDLNs to see if certain EDLNs will serve as good interconnection networks. In this paper作者: Champion 時間: 2025-3-25 10:21 作者: DECRY 時間: 2025-3-25 13:57 作者: 適宜 時間: 2025-3-25 16:30
Anvesha Amaravati,Manan Chugh,Arijit Raychowdhuryloring with fixed number of colors [Bonomo, Mattia and Oriolo, 2011]..In this work we present a constructive .-time algorithm to compute the thinness for any given .-vertex tree, along with a corresponding thin representation. We use intermediate results of this construction to improve known bounds 作者: 吹牛需要藝術(shù) 時間: 2025-3-25 23:46
Chun-Jen Tsai,Tsung-Han Wu,Hung-Cheng Su,Cheng-Yang Chen of the OSD-codes with another well-studied code in the literature called open locating dominating codes, or OLD-codes for short, we compare the two on various graph families. Finally, we also provide an equivalent reformulation of the problem of finding OSD-codes of a graph as a covering problem in作者: noxious 時間: 2025-3-26 01:43
ra’s algorithm on a graph with . vertices and . edges should take .(.?+?.·log.) time and consequently the Dijkstra procedure for SSSPP using Fibonacci Heaps is optimal, in the comparison-based model. In this paper, we introduce a new data structure to implement priority queues called Two-Level Heap 作者: 或者發(fā)神韻 時間: 2025-3-26 06:15
Xabier Iturbe,Didier Keymeulen,Patrick Yiu,Daniel Berisford,Robert Carlson,Kevin Hand,Emre Ozers Professor at McGill University in Montreal. In 1996, the authors, together with Lászlo Gy?rfi, published the successful text, A Probabilistic Theory of Patter978-1-4612-6527-6978-1-4613-0125-7Series ISSN 0172-7397 Series E-ISSN 2197-568X 作者: Adrenal-Glands 時間: 2025-3-26 09:21
Asim Khan,Muhammad Umar Karim Khan,Muhammad Bilal,Chong-Min Kyungiscussing new theories and applications without much distraction. One of the primary goals of NATO ASIs is to bring together a group of scientists and research 978-3-642-77491-1978-3-642-77489-8Series ISSN 0258-1248 作者: Cabg318 時間: 2025-3-26 16:08 作者: hauteur 時間: 2025-3-26 17:49
VLSI-SoC: Design for Reliability, Security, and Low Power23rd IFIP WG 10.5/IE作者: 窩轉(zhuǎn)脊椎動物 時間: 2025-3-26 22:56 作者: sebaceous-gland 時間: 2025-3-27 02:23
1868-4238 International Conference on Very Large Scale Integration, VLSI-SoC 2015, held in Daejeon, Korea, in October 2015. The 10 papers included in the book were carefully reviewed and selected from the 44 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology a作者: 易發(fā)怒 時間: 2025-3-27 08:01
Electromagnetic Transmission of Intellectual Property Data to Protect FPGA Designs,data is a serious challenge for the hardware security community. In this context, this chapter presents two ultra-lightweight transmitters using side channel leakage based on electromagnetic emanation to send embedded IP identity discreetly and quickly.作者: Institution 時間: 2025-3-27 10:45
Conference proceedings 2016he 44 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about new challenges both at the physical and system-design levels, as well as in the test of these systems.作者: 顯示 時間: 2025-3-27 17:04 作者: 出汗 時間: 2025-3-27 18:07 作者: 努力趕上 時間: 2025-3-28 01:53
A SAR Pipeline ADC Embedding Time Interleaved DAC Sharing for Ultra-low Power Camera Front Ends,ving 4X throughput as compared to traditional architectures. Simulations on a 130?nm foundry process shows that the proposed SAR Pipeline ADC draws 31?.W at 2?MS/s having a target Figure-of-Merit (FOM) of 87?fJ/conv. per step at Nyquist rate. The proposed compressive sensing front end achieves per patch energy per patch of 0.9?nJ.作者: 拱墻 時間: 2025-3-28 04:44 作者: thalamus 時間: 2025-3-28 07:20
On the Use of System-on-Chip Technology in Next-Generation Instruments Avionics for Space Exploratiin a single silicon chip (e.g., microprocessor + programmable logic). This chapter discusses the implications of using this technology in deep-space exploration avionics, namely in the next generation of NASA science instruments that will be used to explore our Solar system. We present here our expe作者: 催眠 時間: 2025-3-28 14:08 作者: 榮幸 時間: 2025-3-28 14:37 作者: 波動 時間: 2025-3-28 18:56
Wearable ECG SoC for Wireless Body Area Networks: Implementation with Fuzzy Decision Making Chip,nsor Networks (WBSN) applications. The developed device is portable, wearable, long battery life, and small in size. The device comprises two designed chips, ECG System-on-Chip and Fuzzy Decision Maker chip. The ECG on-chip contains an analog front end circuit and a 12-bit SAR ADC for signal conditi作者: angina-pectoris 時間: 2025-3-28 22:58 作者: BET 時間: 2025-3-29 03:57
