標(biāo)題: Titlebook: VLSI Design and Test; 17th International S Manoj Singh Gaur,Mark Zwolinski,Adit D. Sing Conference proceedings 2013 Springer-Verlag Berlin [打印本頁] 作者: 愚蠢地活 時間: 2025-3-21 17:57
書目名稱VLSI Design and Test影響因子(影響力)
書目名稱VLSI Design and Test影響因子(影響力)學(xué)科排名
書目名稱VLSI Design and Test網(wǎng)絡(luò)公開度
書目名稱VLSI Design and Test網(wǎng)絡(luò)公開度學(xué)科排名
書目名稱VLSI Design and Test被引頻次
書目名稱VLSI Design and Test被引頻次學(xué)科排名
書目名稱VLSI Design and Test年度引用
書目名稱VLSI Design and Test年度引用學(xué)科排名
書目名稱VLSI Design and Test讀者反饋
書目名稱VLSI Design and Test讀者反饋學(xué)科排名
作者: IDEAS 時間: 2025-3-21 23:22 作者: engrave 時間: 2025-3-22 01:29 作者: oracle 時間: 2025-3-22 05:55
Impact of Fin Width and Graded Channel Doping on the Performance of 22nm SOI FinFET,fin width to be scaled beyond 10nm. Stability of the fins patterned beyond 10nm width is to be viewed with suspected eyes. It is observed that Graded doping of the channel will improve threshold voltage and hence the ratio of I. to ..will also increase, which is desired for enhanced performance in analog applications.作者: 單色 時間: 2025-3-22 08:47
1865-0929 ubmissions. The papers discuss the frontiers of design and test of VLSI components, circuits and systems. They are organized in topical sections on VLSI design, testing and verification, embedded systems, emerging technology.978-3-642-42023-8978-3-642-42024-5Series ISSN 1865-0929 Series E-ISSN 1865-0937 作者: 敘述 時間: 2025-3-22 13:56
A Novel Design Methodology for High Tuning Linearity and Wide Tuning Range Ring Voltage Controlled uration region during switching and consequently enhances the tuning range without additional circuitry. The design is implemented in UMC 0.18 .m CMOS technology at 1.8 V supply voltage. The overall circuit consumes 260 .W power at 404.5 MHz, has a wide tuning range of 66 MHz to 875 MHz having 94.5% tuning linearity.作者: Morbid 時間: 2025-3-22 19:00 作者: FACT 時間: 2025-3-22 23:31 作者: Mercantile 時間: 2025-3-23 03:23 作者: 名詞 時間: 2025-3-23 09:12 作者: NEX 時間: 2025-3-23 12:18
Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Submperature ranging from 0.C to 100.C are investigated. The 32-bit adder is simulated using Spectre Simulator in Cadence environment. Finally, Monte-Carlo Simulation was done to calculate the worst case delay for 180nm CMOS Technology.作者: 淡紫色花 時間: 2025-3-23 14:06
Characterization of Logical Effort for Improved Delay,wed gate, high and low skewed gates, whereas, an improvement of 20% - 25% when compared to skewed gates favoring a particular transition. All simulations are done using Spectre in Cadence environment in UMC90nm CMOS technology at 1V power supply.作者: auxiliary 時間: 2025-3-23 20:25
An Ultra-Wideband Baseband Transmitter Design for Wireless Body Area Network,plexity transmitter controller and an efficient algorithm for determining the interleaver size has been implemented. Two different architectures have been implemented in 0.13 .m CMOS technology which are operated at 487.5 kHz system clock with 1.08 V supply.作者: Prostaglandins 時間: 2025-3-24 01:06
Design and Simulation of Bulk Micromachined Accelerometer for Avionics Application,y calculated. For 10g acceleration the relative resistance change is 3.66 × 10. and output voltage is 18.29 mV. Sensitivity of this accelerometer is 0.366 mV/V/g. A comparison of the analytical and simulation results is also presented.作者: AMITY 時間: 2025-3-24 06:05 作者: maudtin 時間: 2025-3-24 07:33 作者: characteristic 時間: 2025-3-24 14:26
Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM,e Amplifier (SA) stability deterioration is another problem in low-voltage operation. These phenomena occur because the random transistor variation becomes larger as the process scaling progresses. In this work a highly robust and novel Ultra-High-Speed (UHS) hybrid current/voltage sensing technique作者: bleach 時間: 2025-3-24 15:36 作者: 增強(qiáng) 時間: 2025-3-24 22:32
An Ultra-Wideband Baseband Transmitter Design for Wireless Body Area Network,architecture for UWB PHY is implemented according to the standard IEEE 802.15.6. Since WBAN is the network around the humanbody there are stringent requirements associated with it such as high security, low power consumption and reliable communication. To incorporate these features in baseband trans作者: Neonatal 時間: 2025-3-25 01:36 作者: outer-ear 時間: 2025-3-25 06:10 作者: maroon 時間: 2025-3-25 11:34 作者: hegemony 時間: 2025-3-25 11:59
Kapees: A New Tool for Standard Cell Placement,sign that in turn results into minimal routed wire length and thus wire delay. We describe a new method, ., for large scale standard cell placement. Our technique is based on recursive partitioning of placement circuit which is modeled as a hypergraph. It uses partitioning during the global placemen作者: 安定 時間: 2025-3-25 19:12
Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization,rallelism and scalability. To reduce the testing cost of such a system, the existing communication structure ca be reused. In this paper, we have proposed a Particle Swarm Optimization (PSO) based mixed test scheduling approach to test the cores in the NoC environment. It incorporates both non-preem作者: byline 時間: 2025-3-25 22:43
Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence,tching activity on the address bus of the on-chip data memory, with the help of loop unrolling with partial Gray code sequence. The present work introduces the translation of a loop with array initialization to its loop unrolled version with partial Gray code sequence. The expressions for switching 作者: Accomplish 時間: 2025-3-26 01:42 作者: heterodox 時間: 2025-3-26 07:05 作者: Flatter 時間: 2025-3-26 08:54
Characterization of Logical Effort for Improved Delay,l effort has been derived for universal logic gates namely NOT, NAND and NOR for minimizing the delay. The validations for minimum delay through simulation was done on a chain of inverters. The improved skewed gates showed 10% - 20% delay reduction on a chain of inverters as compared with normal ske作者: TATE 時間: 2025-3-26 13:22
A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance,) symmetric double-gate junctionless transistor (DGJLT). The characteristics are demonstrated and compared with dual material gate (DMG) DGJLT and single material (conventional) gate (SMG) DGJLT. DMG DGJLT present superior transconductance (G.), early voltage (V.) and intrinsic gain (G.R.) compared 作者: 客觀 時間: 2025-3-26 18:10 作者: Obstreperous 時間: 2025-3-26 22:08
An Efficient RF Energy Harvester with Tuned Matching Circuit,er earlier matching circuit. This paper presents an RF energy harvester with microstrip line in series with tuned .-matching circuit that enables efficient power conversion at different RF input power under different load conditions. Matching circuit parameters were optimized for better efficiency. 作者: overwrought 時間: 2025-3-27 02:29 作者: ingrate 時間: 2025-3-27 07:02 作者: 野蠻 時間: 2025-3-27 13:07 作者: 外貌 時間: 2025-3-27 15:21
1865-0929 osium on VLSI Design and Test, VDAT 2013, held in Jaipur, India, in July 2013. The 44 papers presented were carefully reviewed and selected from 162 submissions. The papers discuss the frontiers of design and test of VLSI components, circuits and systems. They are organized in topical sections on VL作者: PALL 時間: 2025-3-27 18:19 作者: 熒光 時間: 2025-3-27 22:45
Rahul Krishnamurthy,G. K. Sharmaen entnehmen, welche über die Jahrtausende hinweg bis zur Gegenwart Geltung haben. Die Weissagung über Ismael (I. Mose 16, 12): Er wird ein Mensch wie ein Wildesel sein — seine Hand wider jedermann und jedermanns Hand wider ihn —, trifft zu. Die Kapitel 6–8 des Richterbuches schildern einen typische作者: Granular 時間: 2025-3-28 02:33 作者: Condescending 時間: 2025-3-28 07:43
Amit Sharma,Ravindra Mukhiya,S. Santosh Kumar,B. D. Pant), trotzdem sind unsere bisherigen Kenntnisse über die Bedeutung des Fluors für die Pflanzen aber sehr unbefriedigend, und es besteht lediglich einige Klarheit über die Rolle, die das Fluor im tierischen bezw. menschlichen Stoffwechsel spielt. Da das Fluor einen Teil der Hydroxylgruppen im Hydroxyla作者: 一再遛 時間: 2025-3-28 14:20
Himadri Singh Raghav,Sachin Maheshwari,B. Prasad Singht nur die Interpretation der Ergebnisse der Arbeit, sondern erm?glicht erst die Einbettung in den Forschungsstand. Ziel dieses zweiten Kapitels ist es demnach, dem Leser den Gegenstand der vorliegenden Arbeit – das Konstrukt . – n?herzubringen. Dieses Unterfangen gestaltet sich bei vielen Konstrukte作者: 水獺 時間: 2025-3-28 17:27 作者: 空氣 時間: 2025-3-28 19:28 作者: 暫時中止 時間: 2025-3-29 00:53 作者: 高深莫測 時間: 2025-3-29 06:02 作者: 斷言 時間: 2025-3-29 10:29
,Computational Functions’ VLSI Implementation for Compressed Sensing,ious computational functions useful in realizing CS recovery consisting of Singular Value Decomposition (SVD) using Bi-diagonalization method; L.norm of vector, L. norm of vector calculations. This is one of the early VLSI implementation attempt for CS recovery. We have verified the design for speed and accuracy of results on FPGA.作者: 知識 時間: 2025-3-29 13:02 作者: braggadocio 時間: 2025-3-29 19:12 作者: PURG 時間: 2025-3-29 21:26
https://doi.org/10.1007/978-3-642-42024-5SRAM arrays; VLSI; digital circuits; multi-processor architectures; network-on-chip作者: Anhydrous 時間: 2025-3-30 02:49
A Low-Power Wideband High Dynamic Range Single-Stage Variable Gain Amplifier,This paper presents a low-voltage, low-power, wideband, single-stage variable gain amplifier (VGA) that provides a 57-dB gain variation. It consumes 1.35 mW, which is one of the lowest power consumptions reported for similar VGAs in the literature. The 3-dB bandwidth varies from 110 MHz at 25 dB gain to 3.8 GHz at -32 dB gain.作者: CAMEO 時間: 2025-3-30 06:25 作者: FEIGN 時間: 2025-3-30 09:59 作者: Encapsulate 時間: 2025-3-30 15:11 作者: 云狀 時間: 2025-3-30 16:39 作者: 雜色 時間: 2025-3-30 23:49 作者: Adrenal-Glands 時間: 2025-3-31 01:02 作者: Leaven 時間: 2025-3-31 06:35 作者: macular-edema 時間: 2025-3-31 09:23
Kanchan Manna,Shailesh Singh,Santanu Chattopadhyay,Indranil Sengupta作者: corn732 時間: 2025-3-31 16:18
Sachin Agrawal,Sunil Pandey,Jawar Singh,P. N. Kondekar作者: Rotator-Cuff 時間: 2025-3-31 18:34 作者: BILIO 時間: 2025-4-1 00:11
R. K. Naga Mahesh,Akash Ganesan,Manchi Pavan Kumar,Roy Pailye Str?mungsprofil dieses Gases erkl?ren. Im Einzelfall, bei stark erh?hten Atemvolumina, waren die beschriebenen Unterschiede noch gr??er. Wegen der geringen Stichprobenzahl der Patienten ohne Verletzungen der Lungen oder des Thorax konnte der erwartungsgem?? geringere Unterschied nicht statistisch 作者: Asymptomatic 時間: 2025-4-1 03:03 作者: 軟膏 時間: 2025-4-1 06:29
Sameer Pawanekar,Kalpesh Kapoor,Gaurav Trivedinnen aber für die Gesundheitsverh?ltnisse in den Betrieben erh?hte Wichtigkeit, weil der Mensch im erwerbsf?higen Alter mindestens den dritten Teil seines Daseins an den St?tten der Arbeit zubringt und weil gerade hier seine besten Kr?fte t?glich von neuem in Anspruch genommen werden. Die Hygiene ha作者: spinal-stenosis 時間: 2025-4-1 11:30 作者: insincerity 時間: 2025-4-1 15:50
Himadri Singh Raghav,Sachin Maheshwari,B. Prasad Singh, Stearns 1993). Der Anspruch des folgenden Unterkapitels kann es deshalb nicht sein, Fragen der Emotionsforschung zu beantworten, die z.T. schon auf Sokrates zurückgehen (vgl. Solomon 1993 S. 3). Vielmehr soll das der Arbeit zugrundeliegende Verst?ndnis des Untersuchungsgegenstandes offengelegt und作者: indubitable 時間: 2025-4-1 20:45 作者: DNR215 時間: 2025-4-1 23:52
