標題: Titlebook: VLSI Design and Test; 21st International S Brajesh Kumar Kaushik,Sudeb Dasgupta,Virendra Sing Conference proceedings 2017 Springer Nature S [打印本頁] 作者: VERSE 時間: 2025-3-21 18:56
書目名稱VLSI Design and Test影響因子(影響力)
書目名稱VLSI Design and Test影響因子(影響力)學科排名
書目名稱VLSI Design and Test網絡公開度
書目名稱VLSI Design and Test網絡公開度學科排名
書目名稱VLSI Design and Test被引頻次
書目名稱VLSI Design and Test被引頻次學科排名
書目名稱VLSI Design and Test年度引用
書目名稱VLSI Design and Test年度引用學科排名
書目名稱VLSI Design and Test讀者反饋
書目名稱VLSI Design and Test讀者反饋學科排名
作者: 影響帶來 時間: 2025-3-21 20:40 作者: 連接 時間: 2025-3-22 01:17
K. Dheepika,K. S. Jevasankari,Vippin Chandhar,Binsu J. Kailathbreitenden Bahnnetzes den Welthandel an sich rissen und die daran dachten, welche Frachten in der Zeit vor der Errichtung der Eisenbahnen bestanden hatten, dachten kaum daran, sich sehr ernstlich zu beschweren. Die Gesetze blieben aber stets im Gesetzbuche aufrecht und als dem gro?en Auf- schwung de作者: 濃縮 時間: 2025-3-22 05:03 作者: 狗窩 時間: 2025-3-22 08:59
Jatindeep Singh,Satyajit Mohapatra,Nihar Ranjan Mohapatraulich, wenn man ihn mit der rein mechanischen L?sung eines festen K?rpers vergleicht. Sowie letzterer, um in den flüssigen Zustand überzugehen, der Umgebung W?rme entzieht und daher, so zu sagen, K?lte hinterl??t, so nehmen die sich ionisierenden Metallatome die erforderlichen positiven elektrischen作者: 切割 時間: 2025-3-22 15:18 作者: 多樣 時間: 2025-3-22 17:21
Naresh Kumar,Raja Hari Gudlavalleti,Subash Chandra Bose23). In der Reaktionsl?sung treffen die DNA-Einzelstr?nge zuf?llig aufeinander. Sind komplement?re Sequenzen im Bereich der sich treffenden Str?nge, bildet sich ein kurzer doppelstr?ngiger Abschnitt, der sich dann reissverschlussartig über den Rest des komplement?ren Moleküls ausdehnt. Die Renaturie作者: 鉆孔 時間: 2025-3-22 23:02
M. Santosh,Anjli Bansal,Jitendra Mishra,K. C. Behra,S. C. Bose23). In der Reaktionsl?sung treffen die DNA-Einzel-str?nge zuf?llig aufeinander. Sind komplement?re Sequenzen im Bereich der sich treffenden Str?nge, bildet sich ein kurzer doppelstr?ngiger Abschnitt, der sich dann reissverschlussartig über den Rest des komplement?ren Moleküls ausdehnt. Die Renaturi作者: Liability 時間: 2025-3-23 02:19 作者: Plaque 時間: 2025-3-23 07:42 作者: 戰(zhàn)勝 時間: 2025-3-23 13:38 作者: 玉米 時間: 2025-3-23 14:10 作者: Bombast 時間: 2025-3-23 19:50
FEM Based Device Simulator for High Voltage Devicessed proposed simulator with conventional available device simulator. A simple . junction diode is designed in both the simulators and a comparison of different electrical properties has been done by incorporating similar models and exactly same material parameters.作者: Rotator-Cuff 時間: 2025-3-23 23:18
Synapse Circuits Implementation and Analysis in 180?nm MOSFET and CNFET Technologyin literature. We have ported these circuits to 180?nm MOSFET technology and CNFET technology and studied their response in terms of their functionality, the average power consumption and area occupancy. The simulations in this work have been carried out using HSPICE software.作者: 得罪 時間: 2025-3-24 03:47 作者: 頌揚國家 時間: 2025-3-24 10:24 作者: 沙漠 時間: 2025-3-24 10:40
K. Dheepika,K. S. Jevasankari,Vippin Chandhar,Binsu J. Kailathnnahme, da? die parlamentarischen Schemen der frühen Zeit, wenigstens soweit sie den Güterverkehr betrafen, veraltet waren, bevor sie noch Gesetz wurden. Sicherlich veralteten sie bald. Sie wurden vergessen oder stillschweigend nicht beachtet, wie viele andere Gesetze, die im Gesetzbuche fortleben, 作者: 預兆好 時間: 2025-3-24 18:35
Pravin Zode,R. B. Deshmukh,Abdus Samad80 cm lange und etwa 1 cm weite Glasr?hre mit luftfreiem Quecksilber zu füllen, sie in einer Quecksilberwanne umzukehren und alsdann in ihr ein ungef?hr 1 cm. grosses Fl?schchen aufsteigen zu lassen, welches ganz mit der zu prüfenden Flüssigkeit gefüllt und mit einem lose aufgesetzten Glasst?psel ve作者: 迅速飛過 時間: 2025-3-24 19:02 作者: mettlesome 時間: 2025-3-25 02:15 作者: 空氣 時間: 2025-3-25 07:16
Naresh Kumar,Raja Hari Gudlavalleti,Subash Chandra Bose künstlich im Labor, also in vitro, kann man dies erzeugen. Durch einfache Temperaturerh?hung auf 95°C werden die Wasserstoffbrücken zwischen den Basen destabilisiert, dies führt dann in der Folge zur Aufl?sung der Doppelhelix zu Einzelstr?ngen. Diesen in vitro-Vorgang nennt man wissenschaftlich Den作者: 激怒某人 時間: 2025-3-25 08:52 作者: paroxysm 時間: 2025-3-25 13:54
Ashok Ray,Gaurav Kumar,Sushanta Bordoloi,Dheeraj Kumar Sinha,Pratima Agarwal,Gaurav Trivedi seinen Abh?ngen gediehen auf dem kali- und phosphorreichen Verwitterungsboden alter Laven üppige Obstg?rten, zu seinen Fü?en lagen reiche St?dte mit sch?nen S?ulenhallen, und niemand ahnte etwas von den dunklen Gewalten der Tiefe, bis pl?tzlich im Jahre 79 v. Chr. jener gewaltige Ausbruch erfolgte,作者: d-limonene 時間: 2025-3-25 17:19 作者: Analogy 時間: 2025-3-25 22:41 作者: extinguish 時間: 2025-3-26 01:13
Conference proceedings 2017ganized in topical sections named: digital design; analog/mixed signal; VLSI testing; devices and technology; VLSI architectures; emerging technologies and memory; system design; low power design and test; RF circuits; architecture and CAD; and design verification..作者: 嚙齒動物 時間: 2025-3-26 06:43
1865-0929 , VDAT 2017, held in Roorkee, India, in June/July 2017.. The 48 full papers presented together with 27 short papers were carefully reviewed and selected from 246 submissions. The papers were organized in topical sections named: digital design; analog/mixed signal; VLSI testing; devices and technolog作者: 外觀 時間: 2025-3-26 12:29 作者: 偽善 時間: 2025-3-26 14:32
A New Multi-objective Hardware-Software-Partitioning Algorithmic Approach for High Speed Applicationn proposed which also takes into consideration the communication costs between hardware and software Processing-Engines (PEs) while partitioning. Detailed empirical analysis of the proposed algorithm is presented to ascertain its efficiency, quality and speed.作者: 榮幸 時間: 2025-3-26 20:10
An Improved Highly Efficient Low Input Voltage Charge Pump Circuital architecture, this modification has reduced the voltage loss at the output to 1.3% as compared to 9% for 1?V input and 6% as compared to 20% for 0.3?V input voltage. The core dimension of the layout is 750?μm?×?530?μm.作者: 跟隨 時間: 2025-3-26 22:37
VLSI Implementation of Throughput Efficient Distributed Arithmetic Based LMS Adaptive Filter shown that the proposed scheme occupies almost similar area and improves the throughput by several fold. For instance, a 32- tap adaptive filter with the proposed implementation produces nearly 1.8 MSPS (million samples per second) more throughput as compared to the best existing scheme.作者: Electrolysis 時間: 2025-3-27 02:48
Performance Optimized 64b/66b Line Encoding Technique for High Speed SERDES Devicesrmance optimum between security, run-length, ISI and DC equalization, this scheme finds potential application in space camera electronics, 5G technology and other IOT applications like driverless cars that require to handle large volumes of real time data with sufficient security on high BER wireless channels.作者: Excitotoxin 時間: 2025-3-27 07:15
FPGA Implementation of a Novel Area Efficient FFT Scheme Using Mixed Radix FFT is found that the hardware requirement for the proposed approach reduces by 25%–53% at the cost of speed compared to the other schemes reported in the literature including that using only R2MDC architecture. The proposed scheme is preferred for low sampling rate applications such as biomedical signal processing.作者: 不真 時間: 2025-3-27 10:56 作者: Curmudgeon 時間: 2025-3-27 15:52 作者: Catheter 時間: 2025-3-27 21:30
Estimating the Maximum Propagation Delay of 4-bit Ripple Carry Adder Using Reduced Input Transitions, etc. Due to the crucial role of adder in arithmetic unit, it is necessary to satisfactorily characterize the maximum propagation delay of the adder. To characterize 4-bit Ripple Carry Adder (RCA), ideally 261,632 input transitions are required [.], which is a humongous number. In this paper, we ha作者: 概觀 時間: 2025-3-28 00:18
VLSI Implementation of Throughput Efficient Distributed Arithmetic Based LMS Adaptive Filter02.11b PHY scenarios. It is based on pre-computing and storing the filter partial products in lookup tables (LUTs). In contrast to fixed coefficients filter, an adaptive filter requires each stored partial product to be updated time-to-time. This paper presents a new strategy for DA based adaptive f作者: Pathogen 時間: 2025-3-28 02:48
Realization of Multiplier Using Delay Efficient Cyclic Redundant Addergeneration is propounded in this paper. A Multiplier based on Quarter square algorithm is designed and implemented using the proposed Cyclic Redundant Adder on Field Programmable Gate Array. The proposed Cyclic Redundant adder is compared amongst the recent high performance adders like Ling Adder, C作者: Noctambulant 時間: 2025-3-28 09:15 作者: Absenteeism 時間: 2025-3-28 13:43 作者: Criteria 時間: 2025-3-28 14:51 作者: gruelling 時間: 2025-3-28 22:36
A Framework for Branch Predictor Selection with Aggregation on Multiple Parameters execution play a key role in predictor selection. The task of selecting the best predictor considering all the different parameters, is therefore, a non-trivial one, and is considered one of the foremost challenges. In this paper, we present a framework that systematically addresses this important 作者: NICE 時間: 2025-3-29 01:49 作者: 火海 時間: 2025-3-29 06:26
Low Voltage, Low Power Transconductor for Low Frequency ,-C FiltersC 180?nm technology with supply voltage of 0.5?V. The transconductance (.) is tunable from 12?nS to 100?nS, which is suitable for low frequency . filters. The power consumption is 120 nW. As an application, a . order Butterworth low pass filter (LPF) with cutoff frequency tunable from 110?Hz to 960?作者: CHAR 時間: 2025-3-29 07:45
An Improved Highly Efficient Low Input Voltage Charge Pump Circuitstor. This paper proposes an improved dynamic CTS based charge pump circuit by modifying the conventional circuit architecture at the output stage by a PMOS transistor with appropriate control signals. A four-stage dynamic CTS based charge pump circuit with pumping capacitance of 50 pF, clock freque作者: 游行 時間: 2025-3-29 11:33
A Calibration Technique for Current Steering DACs - Self Calibration with Capacitor Storage. To overcome this area accuracy trade off, several calibration techniques were investigated. This paper presents a modified self calibration technique for current-steering (CS) digital-to-analog converters (DACs). In the digital calibration technique calibrating DACs (CALDACs) are connected across 作者: Tremor 時間: 2025-3-29 17:00
Characterization and Compensation Circuitry for Piezo-Resistive Pressure Sensor to Accommodate Temperesistive sensors generally, decreases with the increase in temperature when subjected to constant voltage excitation. To control the change with temperature, a varying excitation method is used. The proposed technique utilizes current steering DACs and a digital controller to compensate the variati作者: antidote 時間: 2025-3-29 23:43 作者: 背信 時間: 2025-3-30 00:54
Synapse Circuits Implementation and Analysis in 180?nm MOSFET and CNFET Technology up these large-scale networks are the neurons and the synapses. The synapses serve as interconnections between the neurons for computation and transfer of information in real as well as artificial neural systems. Synapses in the neuronal networks can be static with a constant gain or dynamic with m作者: Bph773 時間: 2025-3-30 05:32 作者: Chronic 時間: 2025-3-30 08:56
Conference proceedings 2017e/July 2017.. The 48 full papers presented together with 27 short papers were carefully reviewed and selected from 246 submissions. The papers were organized in topical sections named: digital design; analog/mixed signal; VLSI testing; devices and technology; VLSI architectures; emerging technologie作者: 入會 時間: 2025-3-30 14:31 作者: 禁止,切斷 時間: 2025-3-30 18:21 作者: Evocative 時間: 2025-3-30 22:10
978-981-10-7469-1Springer Nature Singapore Pte Ltd. 2017作者: precede 時間: 2025-3-31 03:16
VLSI Design and Test978-981-10-7470-7Series ISSN 1865-0929 Series E-ISSN 1865-0937 作者: verdict 時間: 2025-3-31 07:32 作者: 流行 時間: 2025-3-31 11:36
https://doi.org/10.1007/978-981-10-7470-7Analog/Mixed Signal; Architecture and CAD; Circuits; Design Verification; Devices and Technology – I; Dev作者: neolith 時間: 2025-3-31 13:35
Low Voltage, Low Power Transconductor for Low Frequency ,-C FiltersC 180?nm technology with supply voltage of 0.5?V. The transconductance (.) is tunable from 12?nS to 100?nS, which is suitable for low frequency . filters. The power consumption is 120 nW. As an application, a . order Butterworth low pass filter (LPF) with cutoff frequency tunable from 110?Hz to 960?Hz is designed.
