標(biāo)題: Titlebook: New Algorithms, Architectures and Applications for Reconfigurable Computing; Patrick Lysaght,Wolfgang Rosenstiel Book 2005 Springer-Verlag [打印本頁(yè)] 作者: sustained 時(shí)間: 2025-3-21 16:50
書(shū)目名稱(chēng)New Algorithms, Architectures and Applications for Reconfigurable Computing影響因子(影響力)
書(shū)目名稱(chēng)New Algorithms, Architectures and Applications for Reconfigurable Computing影響因子(影響力)學(xué)科排名
書(shū)目名稱(chēng)New Algorithms, Architectures and Applications for Reconfigurable Computing網(wǎng)絡(luò)公開(kāi)度
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書(shū)目名稱(chēng)New Algorithms, Architectures and Applications for Reconfigurable Computing被引頻次
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書(shū)目名稱(chēng)New Algorithms, Architectures and Applications for Reconfigurable Computing讀者反饋
書(shū)目名稱(chēng)New Algorithms, Architectures and Applications for Reconfigurable Computing讀者反饋學(xué)科排名
作者: 小蟲(chóng) 時(shí)間: 2025-3-21 20:40 作者: RUPT 時(shí)間: 2025-3-22 03:18
Enabling Run-time Task Relocation on Reconfigurable Systemsware/software context switching issues. The infrastructure proved its feasibility by allowing us to design a relocatable video decoder. When implemented on an embedded platform, the decoder performs at 23 frames/s (320 × 240 pixels, 16 bits per pixel) in reconfigurable hardware and 6 frames/s in software.作者: 誘導(dǎo) 時(shí)間: 2025-3-22 07:13 作者: prosthesis 時(shí)間: 2025-3-22 12:08 作者: 完成才會(huì)征服 時(shí)間: 2025-3-22 15:24
IPsec-Protected Transport of HDTV over IPis highly programmable and can support a variety of offload functions. A sample application is described, wherein production-quality HDTV is transported over IP at nearly 900 Mbps, fully secured using IPsec with AES encryption.作者: Original 時(shí)間: 2025-3-22 20:39 作者: superfluous 時(shí)間: 2025-3-22 21:48 作者: Spartan 時(shí)間: 2025-3-23 03:06 作者: affect 時(shí)間: 2025-3-23 06:49
A Low Energy Data Management for Multi-Context Reconfigurable Architecturesthe reconfigurable architecture. The Data Scheduler attempts to optimally exploit this storage, by deciding in which on-chip memory the data have to be stored in order to reduce energy consumption. We also show that a suitable data scheduling could decrease the energy required to implement the dynamic reconfiguration of the system.作者: IRK 時(shí)間: 2025-3-23 12:26
Division in , for Application in Elliptic Curve Cryptosystems on Field Programmable Logictiplication in.(.) requires modular multiplication, division/inversion and addition/subtraction. Division is the most costly operation in terms of speed and is often avoided by performing many extra multiplications. This paper proposes a new divider architecture and FPGA implementations for use in an ECC processor.作者: Inveterate 時(shí)間: 2025-3-23 17:23 作者: 卷發(fā) 時(shí)間: 2025-3-23 21:28
Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systemse hardware parts of an embedded system can be implemented in a hardware byte code, which can be interpreted using a virtual hardware machine running on an arbitrary FPGA. Our results show that this approach is feasible and that it leads to fast, portable and reconfigurable designs, which run on any programmable target architecture.作者: dandruff 時(shí)間: 2025-3-24 01:00 作者: 紡織品 時(shí)間: 2025-3-24 06:01
Fast, Large-scale String Match for a 10 Gbps FPGA-based NIDS frequencies in excess of 340 MHz for fast Virtex devices. To increase throughput, we use multiple comparators and allow for parallel matching of multiple search strings. We evaluate the area and latency cost of our approach and find that the match cost per search pattern character is between 4 and 5 logic cells.作者: HPA533 時(shí)間: 2025-3-24 07:31
hat span the traditional boundaries of electronic engineerin.New Algorithms, Architectures and Applications for Reconfigurable Computing. consists of a collection of contributions from the authors of some of the best papers from the Field Programmable Logic conference (FPL’03) and the Design and Tes作者: Additive 時(shí)間: 2025-3-24 13:15
A Unified Codesign Environmentlications. A codesign environment with automatic partitioning and scheduling between a host processor and a number of reconfigurable coprocessors is described. A unified runtime environment for both hardware and software tasks under the control of a task manager is proposed. The practicality of our system is demonstrated with an FFT application.作者: SKIFF 時(shí)間: 2025-3-24 16:01 作者: 平靜生活 時(shí)間: 2025-3-24 22:12 作者: CLAP 時(shí)間: 2025-3-25 01:51
http://image.papertrans.cn/n/image/664770.jpg作者: 共同生活 時(shí)間: 2025-3-25 03:27 作者: 凝結(jié)劑 時(shí)間: 2025-3-25 07:45 作者: Deference 時(shí)間: 2025-3-25 13:02 作者: Flatus 時(shí)間: 2025-3-25 16:05 作者: indifferent 時(shí)間: 2025-3-25 23:42
Herman Schmitre accurate computation of the Miller factor is derived. To achieve both computational efficiency and accuracy, a variety of mechanisms for pruning the search space are detailed, including: .-Spatial pruning - reducing aggressors to those in physical proximity, .-Electrical pruning - reducing aggressors by el978-1-4757-7949-3978-1-4020-8092-0作者: JIBE 時(shí)間: 2025-3-26 04:13 作者: 有節(jié)制 時(shí)間: 2025-3-26 05:02 作者: 別名 時(shí)間: 2025-3-26 10:24
Unai Bidarte,Armando Astarloa,Aitzol Zuloaga,José Luis Martín,Jaime Jiménezre accurate computation of the Miller factor is derived. To achieve both computational efficiency and accuracy, a variety of mechanisms for pruning the search space are detailed, including: .-Spatial pruning - reducing aggressors to those in physical proximity, .-Electrical pruning - reducing aggressors by el978-1-4757-7949-3978-1-4020-8092-0作者: ARK 時(shí)間: 2025-3-26 12:59
A Tightly Coupled VLIW/Reconfigurable Matrix and its Modulo Scheduling Technique作者: 秘傳 時(shí)間: 2025-3-26 18:43
Dynamic and Partial Reconfiguration in FPGA SoCs: Requirements Tools and a Case Study作者: 絕食 時(shí)間: 2025-3-27 00:38
Architecture and FPGA Implementation of a Digit-serial RSA Processor作者: 夸張 時(shí)間: 2025-3-27 01:23
New Algorithms, Architectures and Applications for Reconfigurable Computing作者: 是突襲 時(shí)間: 2025-3-27 06:14 作者: Mri485 時(shí)間: 2025-3-27 13:07
yption applications...Field programmable logic and reconfigurable computing are exciting research disciplines that span the traditional boundaries of electronic engineering and computer science. When the skills978-1-4419-5264-6978-1-4020-3128-1作者: covert 時(shí)間: 2025-3-27 13:42 作者: 群居男女 時(shí)間: 2025-3-27 20:04
Yuanqing Guo,Gerard J.M. Smit,Michèl A.J. Rosien,Paul M. Heysters,Thijs Krol,Hajo Broersma作者: 腐蝕 時(shí)間: 2025-3-27 22:43 作者: 提名的名單 時(shí)間: 2025-3-28 04:37 作者: 合唱團(tuán) 時(shí)間: 2025-3-28 07:02 作者: OUTRE 時(shí)間: 2025-3-28 12:08
Peter Bellows,Jaroslav Flidr,Ladan Gharai,Colin Perkins,Pawel Chodowiec,Kris Gaj作者: 桶去微染 時(shí)間: 2025-3-28 16:01
Alessandro Cilardo,Antonino Mazzeo,Luigi Romano,Giacinto Paolo Saggese作者: 鄙視讀作 時(shí)間: 2025-3-28 22:26
Alan Daly,William Marnane,Tim Kerins,Emanuel Popovici作者: GRACE 時(shí)間: 2025-3-29 01:05 作者: Panacea 時(shí)間: 2025-3-29 03:22
Extra-dimensional Island-Style FPGAslike traditionally tiled FPGAs. The proposal uses logical third and fourth dimensions to create increasing wire density for increasing logic capacity. The additional dimensions are mapped to standard two-dimensional silicon. This innovation will increase the longevity of a given cell architecture, a作者: 言行自由 時(shí)間: 2025-3-29 10:44 作者: 駭人 時(shí)間: 2025-3-29 14:20 作者: 休戰(zhàn) 時(shí)間: 2025-3-29 17:19
Customizable and Reduced Hardware Motion Estimation Processorsully parameterizable 2-D systolic array structure for full-search block-matching motion estimation and inherit its configurability properties in what concerns the macroblock and search area dimensions and parallelism level. A significant reduction of the hardware resources can be achieved with the p作者: 一罵死割除 時(shí)間: 2025-3-29 20:08 作者: amplitude 時(shí)間: 2025-3-30 01:58
A Unified Codesign Environmentlications. A codesign environment with automatic partitioning and scheduling between a host processor and a number of reconfigurable coprocessors is described. A unified runtime environment for both hardware and software tasks under the control of a task manager is proposed. The practicality of our 作者: freight 時(shí)間: 2025-3-30 07:56
Mapping Applications to a Coarse Grain Reconfigurable Systemchitecture, called MONTIUM. The source code is first translated into a control dataflow graph (CDFG). Then after applying graph clustering, scheduling and allocation on this CDFG, it can be mapped onto the target architecture. High performance and low power consumption are achieved by exploiting max作者: 動(dòng)機(jī) 時(shí)間: 2025-3-30 10:06
Compilation and Temporal Partitioning for a Coarse-grain Reconfigurable Architecture the configure-execute paradigm, the natural paradigm of dynamically reconfigurable computing. This chapter presents a compiler aiming to program the XPP using a subset of the C language. The compiler, apart from mapping the computational structures onto the available resources on the device, splits作者: PET-scan 時(shí)間: 2025-3-30 13:47 作者: 輕率的你 時(shí)間: 2025-3-30 19:33 作者: packet 時(shí)間: 2025-3-30 23:59
A Low Energy Data Management for Multi-Context Reconfigurable Architecturesnd DSP applications. The main goal of this technique is to diminish application energy consumption. Two levels of on-chip data storage are assumed in the reconfigurable architecture. The Data Scheduler attempts to optimally exploit this storage, by deciding in which on-chip memory the data have to b作者: 江湖騙子 時(shí)間: 2025-3-31 01:06 作者: 點(diǎn)燃 時(shí)間: 2025-3-31 07:15
IPsec-Protected Transport of HDTV over IPerforms security protocols such as IPsec; the additional load of complex cryptographic transforms overwhelms modern CPUs when data rates exceed 100 Mbps. This paper describes a network-processing accelerator which overcomes these bottlenecks by offloading packet processing and cryptographic transfor作者: 帽子 時(shí)間: 2025-3-31 11:08 作者: 變形詞 時(shí)間: 2025-3-31 14:08 作者: Neutral-Spine 時(shí)間: 2025-3-31 19:24 作者: 過(guò)時(shí) 時(shí)間: 2025-3-31 22:03
