標題: Titlebook: Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation; 20th International W René Leuken,Gilles Sica [打印本頁] 作者: 積聚 時間: 2025-3-21 16:17
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation影響因子(影響力)
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation影響因子(影響力)學科排名
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation網(wǎng)絡(luò)公開度
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation網(wǎng)絡(luò)公開度學科排名
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation被引頻次
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation被引頻次學科排名
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation年度引用
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation年度引用學科排名
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation讀者反饋
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation讀者反饋學科排名
作者: 豐滿有漂亮 時間: 2025-3-21 23:43 作者: spondylosis 時間: 2025-3-22 02:33 作者: fringe 時間: 2025-3-22 06:49
Dimitris Bekiaris,Antonis Papanikolaou,Christos Papameletis,Dimitrios Soudris,George Economakos,Kiam作者: 發(fā)酵劑 時間: 2025-3-22 12:21 作者: 清醒 時間: 2025-3-22 16:04
Pascal Vivet,Edith Beigne,Hugo Lebreton,Nacer-Eddine Zergainoh作者: 全神貫注于 時間: 2025-3-22 19:01
P. Carazo,R. Apolloni,F. Castro,D. Chaver,L. Pinuel,F. Tirado作者: neolith 時間: 2025-3-22 21:54
Mohsen Raji,Alireza Tajary,Behnam Ghavami,Hossein Pedram,Hamid R. Zarandi作者: opportune 時間: 2025-3-23 04:49
Oussama Elissati,Eslam Yahya,Sébastien Rieubon,Laurent Fesquet作者: Between 時間: 2025-3-23 07:58 作者: 雄辯 時間: 2025-3-23 11:22 作者: 細微差別 時間: 2025-3-23 17:28
Alberto Garcia-Ortiz,Leandro S. Indrusiak an reliance, especially in the areas of consumer encyclopedia. products and basic industrial commodities, In selecting entries, it was my intention to such as steel. This transition creates opportu- provide the reader with a cross section of nities-in the form of new markets and lower terminology of the vari978-94-010-8323-2978-94-009-4107-6作者: 廣口瓶 時間: 2025-3-23 18:07
Bahman Kheradmand-Boroujeni,Christian Piguet,Yusuf Leblebici an reliance, especially in the areas of consumer encyclopedia. products and basic industrial commodities, In selecting entries, it was my intention to such as steel. This transition creates opportu- provide the reader with a cross section of nities-in the form of new markets and lower terminology of the vari978-94-010-8323-2978-94-009-4107-6作者: 政府 時間: 2025-3-24 01:19 作者: 思想流動 時間: 2025-3-24 04:50 作者: 結(jié)束 時間: 2025-3-24 06:44
A Power-Aware Online Scheduling Algorithm for Streaming Applications in Embedded MPSoCr architectures is to optimize the processing resources usage and power consumption to reach a higher energy efficiency. These optimizations are handled by scheduling techniques. To tackle this issue we propose a global online scheduling algorithm for streaming applications. It takes into account da作者: 使迷惑 時間: 2025-3-24 12:34 作者: 膽小懦夫 時間: 2025-3-24 15:07
System Level Power Estimation of System-on-Chip Interconnects in Consideration of Transition Activitnd sufficiently accurate power estimation technique is needed for making the right design decisions..In this paper we present a method for system-level power estimation of interconnection fabrics in Systems-on-Chip. Estimations with simple average assumptions regarding the data stream are compared a作者: cortex 時間: 2025-3-24 20:14 作者: 殺菌劑 時間: 2025-3-25 00:54
An On-Chip Flip-Flop Characterization Circuitesign flows use characterized data of flip-flops for final signoff. Therefore it’s critical to know precisely the accuracy of characterized data with respect to the actual behavior of flip-flops on silicon. An on-chip flip-flop characterization circuit (FCC) has been presented here which gives the a作者: micronutrients 時間: 2025-3-25 06:29 作者: babble 時間: 2025-3-25 09:22
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuitsoes beyond previous analyses in that traditional rankings do not include layout parasitics, which strongly affect both speed and energy and lead to drastic changes in the optimum transistor sizing. For this reason, in this work layout parasitics are included in the circuit design loop by adopting a 作者: Aids209 時間: 2025-3-25 12:42
A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Frameworky wear-out mechanisms, progressively affecting the performance of complex systems. These phenomena progressively deteriorate the electrical characteristics and therefore the delay of interconnects, leading to violations in timing-critical paths. This work estimates the timing impact of Time-Dependen作者: 喊叫 時間: 2025-3-25 16:27
An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAsnnections play a crucial role in modern FPGAs, because they dominate delay, power and area. Multiple-valued logic allows the reduction of the number of interconnections in the circuit, hence can serve as a mean to effectively curtail the impact of interconnections. In this work we propose a new look作者: EXCEL 時間: 2025-3-25 21:34
On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFStial energy provided an adapted control. In this paper we propose a local on-line optimization technique to reduce energy in data-flow architecture, thanks to a Local Power Manager (LPM) using Vdd-Hopping for efficient local DVFS. The proposed control is a hybrid global and local scheme which respec作者: 洞察力 時間: 2025-3-26 01:13
Self-Timed SRAM for Energy Harvesting Systemsg systems tend to provide nondeterministic, rather than stable, power over time. Existing memory systems use delay elements to cope with the problems under different Vdds. However, this introduces huge penalties on performance, as the delay elements need to follow the worst case timing assumption un作者: 油膏 時間: 2025-3-26 05:40
L1 Data Cache Power Reduction Using a Forwarding Predictororder to reduce this power consumption, we propose in this paper a straightforward filtering technique. The mechanism is based on a highly accurate forwarding predictor that determines if a load instruction will take its corresponding data via forwarding from the load-store structure –thus avoiding 作者: labyrinth 時間: 2025-3-26 12:32
Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process Variations introduces a framework for the statistical leakage power minimization of template-based asynchronous circuits considering process variation. We propose a statistical Dual-Vt assignment of asynchronous circuits that considers both the variability in performance and leakage power consumption of a cir作者: senile-dementia 時間: 2025-3-26 15:21
Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring C a C-element and an inverter - and compares the performances of different implementations of this component in terms of speed, power consumption and phase noise. We also proposed a new self-timed ring stage - only composed by a C-element with complementary outputs - which allows us to increase the m作者: 殘廢的火焰 時間: 2025-3-26 19:22
Hermes-A – An Asynchronous NoC Router with Distributed Routingrface that enables communication between router and synchronous processing elements. The ASIC implementation of the router employed standard CAD tools and a specific library of components. Area and timing characteristics for 180nm technology attest the quality of the design, which displays a maximum作者: 平息 時間: 2025-3-26 23:17 作者: Initiative 時間: 2025-3-27 05:11 作者: Narrative 時間: 2025-3-27 07:48
Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comps paper, transistor reordering and dual-Vth techniques are evaluated regarding their efficiency in mitigating the impact of process variations on a set of pulsed flip-flops. It is shown that the conjunct use of the above mentioned techniques can improve delay, energy and EDP yields more than 1.98X, 作者: 丑惡 時間: 2025-3-27 12:08 作者: lethargy 時間: 2025-3-27 13:52 作者: indubitable 時間: 2025-3-27 21:27
Alberto Garcia-Ortiz,Leandro S. Indrusiakmy purpose, so I set about to write one. capable of satisfying its material needs beyond the subsistence level entirely from domestic My first task was to define my terms-tar- iffs, non-tariff barriers, shipping terminology, resources. As a nation‘s technology advances and edu- etc. As this labor pr作者: d-limonene 時間: 2025-3-27 22:03 作者: 梯田 時間: 2025-3-28 03:42 作者: 翅膀拍動 時間: 2025-3-28 07:45
Qin Tang,Amir Zjajo,Michel Berkelaar,Nick van der Meijs, so I set about to write one. capable of satisfying its material needs beyond the subsistence level entirely from domestic My first task was to define my terms-tar- iffs, non-tariff barriers, shipping terminology, resources. As a nation‘s technology advances and edu- etc. As this labor progressed o作者: 廚房里面 時間: 2025-3-28 13:41 作者: 取回 時間: 2025-3-28 17:38 作者: 繞著哥哥問 時間: 2025-3-28 22:45 作者: EXPEL 時間: 2025-3-28 23:47
A Low-Voltage Log-Domain Integrator Using MOSFET in Weak Inversionts for 1pf integrating capacitor and bias current of 20nA, cutoff frequency is 113.4 KHz and power consumption is 45.44nW. Integrator’s Cutoff frequency is tuned from 1.083 KHz to 1.023MHz using variable integrator capacitor value in the range of 10pf-0.1pf.作者: 用手捏 時間: 2025-3-29 04:36
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuitsnovel strategy. The obtained results show that the energy efficiency and the performance of FFs is mainly determined by the regularity of their topology and layout. Finally, the area-delay tradeoff is also analyzed for the first time.作者: 呼吸 時間: 2025-3-29 07:41 作者: inferno 時間: 2025-3-29 13:27
On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFSts throughput and latency constraints. The approach has been fully validated on a real MIMO Telecom application using a SystemC platform instrumented with power estimates. Local DVFS brings 45% power reduction compared to idle mode. When local on-line optimization benefit from computation time variations, 30% extra energy savings can be achieved.作者: Motilin 時間: 2025-3-29 19:32
L1 Data Cache Power Reduction Using a Forwarding Predictorthe data cache access– or it should catch it from the data cache. Our simulation results show that 36% data cache power savings can be achieved on average, with a negligible performance penalty of 0.1%.作者: CANON 時間: 2025-3-29 23:08 作者: Defiance 時間: 2025-3-30 02:09
An Automated Framework for Power-Critical Code Region Detection and Power Peak Optimization of Embedon strategy is chosen and automatically applied to the source code. In comparison to the manual optimization of power peaks, the automatic approach decreases the execution time overhead while only slightly increasing the required code size.作者: 細微的差異 時間: 2025-3-30 04:48 作者: 分離 時間: 2025-3-30 09:53 作者: Firefly 時間: 2025-3-30 16:07 作者: escalate 時間: 2025-3-30 19:23 作者: 要塞 時間: 2025-3-30 21:50
Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Compt of pulsed flip-flops. It is shown that the conjunct use of the above mentioned techniques can improve delay, energy and EDP yields more than 1.98X, 1.62X and 1.99X times, respectively. The yield optimized flip-flop circuits are also comparatively analyzed to identify the best topologies.作者: 該得 時間: 2025-3-31 03:25 作者: OTHER 時間: 2025-3-31 09:07
An On-Chip Flip-Flop Characterization Circuitons or could be operated in functional mode for functional verification. The delay values are calculated by processing the value of time period of oscillator in different modes. The system was fabricated in 40nm CMOS technology and the flip-flop parameters are extracted from it.作者: 指派 時間: 2025-3-31 10:43
An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAsmplementation overcomes previous proposed techniques with simple and efficient CMOS structures. Moreover, results show significant reductions on power consumption and timing in comparison to binary implementations with similar functionality.作者: insipid 時間: 2025-3-31 16:59
Self-Timed SRAM for Energy Harvesting Systems mismatch problems. It can also be used to replace typical delay lines for use in bundled-data memory banks. A 1Kb SI memory bank is implemented based on this method and analysed in terms of the latency and power consumption.作者: CHOP 時間: 2025-3-31 21:18 作者: BET 時間: 2025-3-31 23:25
Conference proceedings 2011oble, France, in September 2010.The 24 revised full papers presented and the 9 extended abstracts were carefully reviewed and are organized in topical sections on design flows; circuit techniques; low power circuits; self-timed circuits; process variation; high-level modeling of poweraware heterogen作者: engagement 時間: 2025-4-1 05:06
978-3-642-17751-4Springer Berlin Heidelberg 2011作者: 新奇 時間: 2025-4-1 06:33 作者: obstinate 時間: 2025-4-1 10:59
Lecture Notes in Computer Sciencehttp://image.papertrans.cn/i/image/468460.jpg作者: Interlocking 時間: 2025-4-1 15:38 作者: cruise 時間: 2025-4-1 19:39
Conference proceedings 2011oble, France, in September 2010.The 24 revised full papers presented and the 9 extended abstracts were carefully reviewed and are organized in topical sections on design flows; circuit techniques; low power circuits; self-timed circuits; process variation; high-level modeling of poweraware heterogeneous designs in SystemC-AMS; and minalogic.
