標(biāo)題: Titlebook: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation; 22nd International W José L. Ayala,Delong Sha [打印本頁] 作者: 新石器時代 時間: 2025-3-21 19:29
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation影響因子(影響力)
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation影響因子(影響力)學(xué)科排名
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation網(wǎng)絡(luò)公開度
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation網(wǎng)絡(luò)公開度學(xué)科排名
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation被引頻次
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation被引頻次學(xué)科排名
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation年度引用
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation年度引用學(xué)科排名
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation讀者反饋
書目名稱Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation讀者反饋學(xué)科排名
作者: Chemotherapy 時間: 2025-3-21 23:37 作者: Pedagogy 時間: 2025-3-22 00:27
Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths,t, only statistical information of the input-stream is needed. The errors of the estimated Hamming and signal distance properties are in the range of 5% to 14% The result of an estimation is available nearly instantaneously since look-up tables are used for implementation.作者: 燈絲 時間: 2025-3-22 04:52
Direct Statistical Simulation of Timing Properties in Sequential Circuits,is is achieved by solving a system of random differential equations (RDE), thus avoiding time-consuming Monte Carlo simulations. The conducted experiments show the accurate calculation of crossing time statistical moments for several sequential cells using 45nm CMOS technology.作者: Ischemic-Stroke 時間: 2025-3-22 11:39 作者: NAVEN 時間: 2025-3-22 15:02
An Extended Metastability Simulation Method for Synchronizer Characterization,on simulation method are unable to predict correct synchronizer parameters in deep sub-micron technologies. We propose an extended simulation method to estimate synchronizer characteristics more reliably and compare the results obtained with other state-of-the-art simulation methods and with measurements of a 65nm LP CMOS test-chip.作者: 無孔 時間: 2025-3-22 18:54 作者: 發(fā)芽 時間: 2025-3-23 00:25
Adaptive Synchronization for DVFS Applications,ncy by evaluating flip-flop synchronization performance dynamically. The proposed design meets a reliability criterion without relying on excessively-conservative synchronizers to accommodate for worst-case performance.作者: Panacea 時間: 2025-3-23 03:19
Muller C-Element Metastability Containment,ult tolerance considerations require relaxing the timing closure. Therefore, this paper studies the vulnerability of asynchronous circuits to metastability at the example of a Muller-C element. Traditional mitigation techniques are applied to this kind of circuits and their fitness for Muller-C elements is analyzed.作者: Intervention 時間: 2025-3-23 07:39 作者: 我怕被刺穿 時間: 2025-3-23 14:15 作者: Cupping 時間: 2025-3-23 21:26
0302-9743 performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization.978-3-642-36156-2978-3-642-36157-9Series ISSN 0302-9743 Series E-ISSN 1611-3349 作者: HACK 時間: 2025-3-23 23:39
Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level,he experimental results show that the proposed method is much faster than the traditional statistical static delay/power analysis (SSTA/SPA) approaches by a factor of 50; the results are also compared with Monte Carlo simulation data for validation purposes, and show an acceptable error rate of within 5%.作者: Gum-Disease 時間: 2025-3-24 02:40 作者: Coronation 時間: 2025-3-24 07:19 作者: Pillory 時間: 2025-3-24 13:07
Conference proceedings 2013astle, UK Spain, in September 2012. The 25 revised full papers presented were carefully reviewed and selected from numerous submissions. The paper feature emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems, including reconfigurabl作者: mechanism 時間: 2025-3-24 15:17
TCP Window Based DVFS for Low Power Network Controller SoC,trollers using the TCP protocol’s unique capability to sense congested networks. Simulations show that it consistently saves at least 10% more energy than work-load only based DVFS throughout various traffic loads and that it nearly doubles the energy saved at various network congestion levels.作者: fluffy 時間: 2025-3-24 21:10
Low Power Implementation of Trivium Stream Cipher,his paper is to evaluate the suitability of this technique and compare the power consumption and the core area of the low power and standard implementations. The results show that the application of the technique reduces power consumption by more than 20% with only a slight penalty in area and operating frequency.作者: Provenance 時間: 2025-3-25 02:25
Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications,This paper describes and experimentally validates a two-phase clock scheme for such MOBILE based ultra-grain pipelines. Up to our knowledge it is the first MOBILE working circuit reported with this interconnection architecture. The proposed interconnection architecture is applied to the design of a 4-bit Carry Look-ahead Adder.作者: 無能力 時間: 2025-3-25 05:27 作者: 翅膀拍動 時間: 2025-3-25 09:57 作者: BINGE 時間: 2025-3-25 13:35
Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level,rformance due to process variation effects. In developing the library a stepwise approach is adopted in which the effects of process variations on the design parameters of interest at the various levels of design abstraction are evaluated, that is from transistor through circuit to architectural lev作者: 全等 時間: 2025-3-25 19:51
Non-invasive Power Simulation at System-Level with SystemC,unctional properties like timing, power consumption, and temperature need to be validated against given requirements on all abstraction levels. For timing and power consumption at RT- and gate-level several techniques are available, but there is still a lack of methods and tools for power estimation作者: 窗簾等 時間: 2025-3-25 20:27 作者: 使苦惱 時間: 2025-3-26 03:00
An Extended Metastability Simulation Method for Synchronizer Characterization,parameters . (resolution time constant) and .. (metastability window). Typically, evaluation of these parameters has been done by empirical rules of thumb or simple circuit simulations to ensure that the synchronizer MTBF is sufficiently long. This paper shows that those rules of thumb and some comm作者: cringe 時間: 2025-3-26 07:53 作者: vascular 時間: 2025-3-26 10:33 作者: 保守 時間: 2025-3-26 13:26
Noise Margin Based Library Optimization Considering Variability in Sub-threshold, MBaud. The challenges at low supply voltages are timing or functional failures due to variability. A common mitigation technique is to apply cell pruning based on stack height or complexity. We present a new variability-aware methodology based on the static unity gain noise margin and its correspon作者: 上流社會 時間: 2025-3-26 17:27 作者: 夸張 時間: 2025-3-26 22:55 作者: 發(fā)怨言 時間: 2025-3-27 01:16
Muller C-Element Metastability Containment, asynchronous circuits it is normally assumed that the handshaking inhibits metastability. This is, however, only true within the timing closure of the circuit and in the absence of external faults. Metastability may well arise in asynchronous circuits when latching external input signals or when fa作者: 治愈 時間: 2025-3-27 06:22
Low Power Implementation of Trivium Stream Cipher,as simulated with Modelsim, and synthesized with Synopsys in three CMOS technologies with different gate lengths: 180nm, 130nm and 90 nm. The aim of this paper is to evaluate the suitability of this technique and compare the power consumption and the core area of the low power and standard implement作者: noxious 時間: 2025-3-27 10:06
A Generic Architecture for Robust Asynchronous Communication Links,The general idea is to use delay-insensitive codes along with error detecting codes to provide resilience against transient faults as well as robustness against delay variations. The presented link architecture is completely generic with respect to the chosen handshake protocols (2-phase/4-phase) an作者: Outwit 時間: 2025-3-27 17:40 作者: ENDOW 時間: 2025-3-27 18:47 作者: hallow 時間: 2025-3-27 23:31 作者: 閑聊 時間: 2025-3-28 04:21 作者: 恃強(qiáng)凌弱 時間: 2025-3-28 09:16 作者: Derogate 時間: 2025-3-28 13:55 作者: palette 時間: 2025-3-28 17:15 作者: 使糾纏 時間: 2025-3-28 22:49 作者: endocardium 時間: 2025-3-29 00:29
https://doi.org/10.1007/978-3-642-36157-9architecture; dynamic power management; networks; sequential circuits; simulation作者: Accomplish 時間: 2025-3-29 06:53 作者: 字謎游戲 時間: 2025-3-29 07:36 作者: 萬靈丹 時間: 2025-3-29 14:23 作者: Cirrhosis 時間: 2025-3-29 17:49 作者: 利用 時間: 2025-3-29 19:44
Masahiro Kondo,Shinichi Nishizawa,Tohru Ishihara,Hidetoshi Onodera作者: RODE 時間: 2025-3-30 01:59
Reef Eilers,Malte Metzdorf,Sven Rosinger,Domenik Helms,Wolfgang Nebel作者: 松果 時間: 2025-3-30 07:41 作者: Fibroid 時間: 2025-3-30 09:53 作者: paleolithic 時間: 2025-3-30 14:43
Javier Rodríguez,Qin Tang,Amir Zjajo,Michel Berkelaar,Nick van der Meijs作者: 原諒 時間: 2025-3-30 17:07
Jordi Pérez-Puigdemont,Antonio Calomarde,Francesc Moll作者: Blood-Vessels 時間: 2025-3-30 23:10 作者: dapper 時間: 2025-3-31 02:37
Pieter Weckx,Nele Reynders,Ilse de Moffarts,Wim Dehaene作者: foreign 時間: 2025-3-31 07:28 作者: Limerick 時間: 2025-3-31 10:24
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation22nd International W作者: Allure 時間: 2025-3-31 16:03 作者: Connotation 時間: 2025-3-31 20:23
A Standard Cell Optimization Method for Near-Threshold Voltage Operations,zed with our standard cells optimized for the 0.6V condition can be reduced by 31% at the best case and by 23% on average compared with those of the same circuits synthesized with the cells optimized for the nominal supply voltage.作者: 陶醉 時間: 2025-3-31 23:24 作者: 北極熊 時間: 2025-4-1 04:54
Some Feasible Studies for Future Researchelche wichtige Rolle HR und andere Transformationsbegleiter spielten. Au?erdem werden Anst??e und Hypothesen für HR formuliert, welche anderen Unternehmen helfen sollen, die Erfolgswahrscheinlichkeit ihrer agilen Reise zu erh?hen.作者: 節(jié)省 時間: 2025-4-1 06:46 作者: enflame 時間: 2025-4-1 12:18 作者: 火海 時間: 2025-4-1 15:05 作者: gastritis 時間: 2025-4-1 20:36 作者: collagen 時間: 2025-4-1 23:16
Ergebnis, herauszugeben. Etwas anderes gilt für beschlagnahmte Gegenst?nde, die nach § 73 Abs. 4 StGB dem Verfall unterliegen. Sie werden vom Insolvenzbeschlag nicht erfasst. Ihre Herausgabe zugunsten der Masse k?nnte jedoch aufgrund wertender überlegungen vertreten werden.作者: 法律 時間: 2025-4-2 06:34
Book 20103rd editionmpletely revised. The bibliography has been updated and expanded as well, now comprising over - teenhundred titles. The background, scope, and plan of the book are outlined in the Introduction, following this preface. Geometric measure theory, functional analysis and dynamical systems provide the ne
