標(biāo)題: Titlebook: Evolvable Systems: From Biology to Hardware; Third International Julian Miller,Adrian Thompson,Terence C. Fogarty Conference proceedings 2 [打印本頁] 作者: 使醉 時間: 2025-3-21 17:01
書目名稱Evolvable Systems: From Biology to Hardware影響因子(影響力)
書目名稱Evolvable Systems: From Biology to Hardware影響因子(影響力)學(xué)科排名
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書目名稱Evolvable Systems: From Biology to Hardware被引頻次
書目名稱Evolvable Systems: From Biology to Hardware被引頻次學(xué)科排名
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書目名稱Evolvable Systems: From Biology to Hardware讀者反饋
書目名稱Evolvable Systems: From Biology to Hardware讀者反饋學(xué)科排名
作者: AGONY 時間: 2025-3-21 20:56 作者: 擁護(hù)者 時間: 2025-3-22 01:55 作者: 爆米花 時間: 2025-3-22 07:56
Evolving Cellular Automata for Self-Testing Hardware, but requires efficient algorithms for the generation of the logic which generates the test vectors applied to the Unit Under Test. This paper addresses the issue of identifying a Cellular Automaton able to generate input patterns to detect stuckat faults inside a Finite State Machine (FSM) circuit.作者: 顯赫的人 時間: 2025-3-22 11:42
Dynamic Optimisation of Non-linear Feed-Forward Circuits,The target technology is FPGA, where the search space of the algorithm is made of the combinational functions computed by cells, of the interconnection topologies and of the interconnections among cells. This circuit is readily applicable to the design of . cache memories, with . tuning of the funct作者: Obliterate 時間: 2025-3-22 14:16 作者: Obliterate 時間: 2025-3-22 17:45 作者: Inoperable 時間: 2025-3-23 00:53
The Intrinsic Evolution of Virtex Devices Through Internet Reconfigurable Logic,sically by downloading a portion of the bitstream that describes the changes from the baseline circuit. This reconfiguration system is achieved through the use of the Xilinx JBits API to identify and extract the changing bitstream. This partial reconfiguration process is very much faster than the pr作者: Stricture 時間: 2025-3-23 03:17
Evolution of Controllers from a High-Level Simulator to a High DOF Robot,ot simulate raw sensor values or actuator commands, rather we model an intermediate software layer which passes processed sensor data to the controller and receives high-level control commands. This allows us to construct a simulator that runs at over 11000 times faster than real time. Using our sim作者: entail 時間: 2025-3-23 08:41
The Evolution of 3-d C.A. to Perform a Collective Behavior Task,collective behavior (NTCB) task. Under a fitness function that is defined as an averaged area in the iterative map, the GA discovers CA rules with quasiperiod-3(QP3) collective behavior and others with period-3. We describe the generational progression of the GA and the synchronization necessary to 作者: 圖表證明 時間: 2025-3-23 13:12
Initial Evaluation of an Evolvable Microwave Circuit,ure of distributed-constant circuits in the microwave range (i.e., over 1 GHz). These circuits are also difficult to adjust for optimum performance, even for experienced engineers. These related problems make development costs of microwave circuits very high. In order to overcome these problems, we 作者: BUST 時間: 2025-3-23 14:22 作者: Extemporize 時間: 2025-3-23 22:00
Towards a Silicon Primordial Soup: A Fast Approach to Hardware Evolution with a VLSI Transistor Arr 16 transistors programmable in their channel dimensions as well as in their connectivity. A genetic algorithm is executed on a PC connected to one or more programmable transistor arrays (PTA). Individuals are represented by a given configuration of the PTA. The fitness of each individual is determi作者: acheon 時間: 2025-3-24 00:15
Understanding Inherent Qualities of Evolved Circuits: Evolutionary History as a Predictor of Fault ts designed by artificial evolution can exhibit very different inherent qualities to those designed by humans using conventional techniques. It is argued that some inherent qualities arising from the evolutionary approach can be beneficial if they are understood. As a case study, the paper seeks to 作者: 高射炮 時間: 2025-3-24 03:46 作者: travail 時間: 2025-3-24 10:09
,A Hardware Implementation of an Embryonic Architecture Using Virtex? FPGAs,teristic of the new cell is the structure of its memory. It is demonstrated that by implementing the memory as a look-up table, it is possible to synthesise an array of 25 cells in one XCV300 device. A frequency divider is presented as example of the application of embryonic arrays. After simulation作者: 沉積物 時間: 2025-3-24 10:43
Everything on the Chip: A Hardware-Based Self-Contained Spatially-Structured Genetic Algorithm for patially-structured evolutionary algorithm that provides significant speedup over conventional serial processing in three ways: (a) efficient hardware-pipelined fitness evaluation of individuals, (b) evaluation of an entire population of individuals in parallel, and (c) elimination of slow off-chip 作者: 招致 時間: 2025-3-24 15:01 作者: 內(nèi)閣 時間: 2025-3-24 19:27 作者: engrave 時間: 2025-3-25 00:04
https://doi.org/10.1007/3-540-46406-9Hardware; artificial neural network; biology; electronics; evolution; neural network; robot; robotics作者: 后來 時間: 2025-3-25 05:49
978-3-540-67338-5Springer-Verlag Berlin Heidelberg 2000作者: 旁觀者 時間: 2025-3-25 09:32
Evolvable Systems: From Biology to Hardware978-3-540-46406-8Series ISSN 0302-9743 Series E-ISSN 1611-3349 作者: 檢查 時間: 2025-3-25 12:07 作者: graphy 時間: 2025-3-25 16:32
https://doi.org/10.1007/978-94-015-9295-6The target technology is FPGA, where the search space of the algorithm is made of the combinational functions computed by cells, of the interconnection topologies and of the interconnections among cells. This circuit is readily applicable to the design of . cache memories, with . tuning of the function during cache operation.作者: DEFER 時間: 2025-3-25 20:09 作者: bile648 時間: 2025-3-26 00:35 作者: irreparable 時間: 2025-3-26 05:14
Ant Colony System for the Design of Combinational Logic Circuits,ity improvement in partially built circuits to compute the distances required by the AS and we consider as optimal those solutions that represent functional circuits with a minimum amount of gates. The proposed methodology is described together with some examples taken from the literature that illustrate the feasibility of the approach.作者: Cupping 時間: 2025-3-26 11:46
Dynamic Optimisation of Non-linear Feed-Forward Circuits,The target technology is FPGA, where the search space of the algorithm is made of the combinational functions computed by cells, of the interconnection topologies and of the interconnections among cells. This circuit is readily applicable to the design of . cache memories, with . tuning of the function during cache operation.作者: Generic-Drug 時間: 2025-3-26 15:46
Towards an Artificial Pinna for a Narrow-Band Biomimetic Sonarhead,transducer. Experiments with ten reflectors showed the problem of phase cancellation in the received echoes. Analysis of phase cancellation suggests more realistic pinna models for future developments.作者: 在駕駛 時間: 2025-3-26 17:14
Comparison between Three Heuristic Algorithms to Repair a Large-Scale MIMD Computer,this framework, we compare a genetic algorithm, a genetic programming algorithm and a simulated annealing algorithm. We show evidences that both genetic algorithms seem to be excellent to solve the problem.作者: Migratory 時間: 2025-3-26 23:31
Julian Miller,Adrian Thompson,Terence C. FogartyIncludes supplementary material: 作者: ABIDE 時間: 2025-3-27 04:02
Lecture Notes in Computer Sciencehttp://image.papertrans.cn/e/image/318091.jpg作者: 使饑餓 時間: 2025-3-27 09:05 作者: 孤僻 時間: 2025-3-27 11:36 作者: Gingivitis 時間: 2025-3-27 14:17 作者: 馬籠頭 時間: 2025-3-27 20:19 作者: BLA 時間: 2025-3-27 23:02
https://doi.org/10.1007/978-94-015-9295-6The target technology is FPGA, where the search space of the algorithm is made of the combinational functions computed by cells, of the interconnection topologies and of the interconnections among cells. This circuit is readily applicable to the design of . cache memories, with . tuning of the funct作者: 發(fā)誓放棄 時間: 2025-3-28 02:33
Fact-Checking Claims, Policies and Parties,orm of a cellular automaton which serves to arbitrate between a number of fixed basis behaviours. Local communication exists between neighbouring legs. Genetic algorithms search for cellular automata whose arbitration results in successful walking gaits. An example simulation of the technique is pre作者: 刪減 時間: 2025-3-28 09:49
Species Extinction and Biodiversitye is described, and results of experiments discussed, for evolving analogue filters using integrator cell models based upon working programmable analogue VLSI cells developed by one of the authors. This, of necessity, involves using feedback interconnects and settings in the range 0.0 – 1.0 which re作者: Gum-Disease 時間: 2025-3-28 11:58
https://doi.org/10.1057/9781137283924sically by downloading a portion of the bitstream that describes the changes from the baseline circuit. This reconfiguration system is achieved through the use of the Xilinx JBits API to identify and extract the changing bitstream. This partial reconfiguration process is very much faster than the pr作者: ARM 時間: 2025-3-28 16:56 作者: 為寵愛 時間: 2025-3-28 22:22 作者: Forsake 時間: 2025-3-29 02:01 作者: 和諧 時間: 2025-3-29 03:54 作者: 占線 時間: 2025-3-29 09:50 作者: 公豬 時間: 2025-3-29 12:34 作者: 全部 時間: 2025-3-29 16:38 作者: 聚集 時間: 2025-3-29 22:20 作者: 細(xì)節(jié) 時間: 2025-3-30 03:02 作者: 抱狗不敢前 時間: 2025-3-30 06:43
Factorization into Degree One Factorssues in this field is the ability to apply these techniques to real physical systems with all the complexities and affordances that such systems present. Here we present a selection of our work each of which advances the richness of the evolutionary substrate in one or more dimensions. We overview r作者: Evocative 時間: 2025-3-30 09:42 作者: Mere僅僅 時間: 2025-3-30 15:25
Evolving Cellular Automata for Self-Testing Hardware,n algorithm, the . algorithm. Experimental results are provided, which show that in most of the standard benchmark circuits the Cellular Automaton selected by the Selfish Gene algorithm is able to reach a Fault Coverage higher that what can be obtained with current engineering practice with comparab作者: 后來 時間: 2025-3-30 17:33
https://doi.org/10.1007/978-1-349-21299-6n algorithm, the . algorithm. Experimental results are provided, which show that in most of the standard benchmark circuits the Cellular Automaton selected by the Selfish Gene algorithm is able to reach a Fault Coverage higher that what can be obtained with current engineering practice with comparab作者: 種族被根除 時間: 2025-3-30 23:41 作者: 誘拐 時間: 2025-3-31 01:17
Propositions and the Philosophy of Languagenition the proposed hardware immune system will learn to differentiate between acceptable and abnormal states and transitions within the ‘immunised’ system. Potential faults can then be flagged and suitable recovery methods invoked to return the system to a safe state.作者: 巨碩 時間: 2025-3-31 05:54
Kevin F. Clancey,Israel Gohbergex FPGA, and find a speedup factor of over 1000 compared to a C implementation of the same system. The general principles behind the system are very scalable, and as FPGAs become even larger in the future, similar systems will provide extremely large speedups over serial processing.作者: 長矛 時間: 2025-3-31 10:54
Automatic Synthesis, Placement, and Routing of an Amplifier Circuit by Means of Genetic ProgrammingThe approach is illustrated using the problem of designing a 60 decibel amplifier. The fitness measure considers the gain, bias, and distortion of the candidate circuit as well as the area occupied by the circuit after the automatic placement and routing.作者: 招人嫉妒 時間: 2025-3-31 15:28
Immunotronics : Hardware Fault Tolerance Inspired by the Immune System,nition the proposed hardware immune system will learn to differentiate between acceptable and abnormal states and transitions within the ‘immunised’ system. Potential faults can then be flagged and suitable recovery methods invoked to return the system to a safe state.作者: Trypsin 時間: 2025-3-31 19:38
Everything on the Chip: A Hardware-Based Self-Contained Spatially-Structured Genetic Algorithm for ex FPGA, and find a speedup factor of over 1000 compared to a C implementation of the same system. The general principles behind the system are very scalable, and as FPGAs become even larger in the future, similar systems will provide extremely large speedups over serial processing.作者: 噱頭 時間: 2025-4-1 00:56 作者: Bumble 時間: 2025-4-1 03:01 作者: BIAS 時間: 2025-4-1 08:10
