標(biāo)題: Titlebook: Enhanced Virtual Prototyping; Featuring RISC-V Cas Vladimir Herdt,Daniel Gro?e,Rolf Drechsler Book 2021 The Editor(s) (if applicable) and T [打印本頁] 作者: Consonant 時(shí)間: 2025-3-21 18:48
書目名稱Enhanced Virtual Prototyping影響因子(影響力)
作者: 挑剔為人 時(shí)間: 2025-3-21 21:51
http://image.papertrans.cn/e/image/311264.jpg作者: 易改變 時(shí)間: 2025-3-22 03:40 作者: abstemious 時(shí)間: 2025-3-22 06:41 作者: MUTE 時(shí)間: 2025-3-22 12:46
https://doi.org/10.1007/978-3-030-28936-2), which is the language of choice to create Virtual Prototypes (VPs). Then, the main concepts of the RISC-V Instruction Set Architecture (ISA) are described. RISC-V is used in several evaluations and case studies in this book and is the ISA implemented in our proposed open-source RISC-V based VP. F作者: 后退 時(shí)間: 2025-3-22 13:52
https://doi.org/10.1007/978-94-6091-478-2the RISC-V ecosystem. The VP provides a 32/64 bit RISC-V core with an essential set of peripherals and support for multi-core simulations. In addition, the VP also provides SW debug (through the Eclipse IDE) and coverage measurement capabilities and supports the FreeRTOS, Zephyr and Linux operating 作者: 后退 時(shí)間: 2025-3-22 17:41 作者: Density 時(shí)間: 2025-3-22 23:21
https://doi.org/10.1057/9780230288843ethods, which may still be susceptible to state space explosion. Compared to the existing simulation-based verification flow this chapter investigates stronger coverage metrics as well as advanced automated test-case generation and refinement techniques. In particular it considers the Data Flow Test作者: Charade 時(shí)間: 2025-3-23 03:11
https://doi.org/10.1057/9780230274907tion flow by integrating stronger coverage metrics and providing automated test-case generation techniques as well as leverage formal methods. Ensuring correct functional behavior is very important to avoid errors and security vulnerabilities (such as buffer overflows). The first approach integrates作者: 放肆的你 時(shí)間: 2025-3-23 09:11
Performance of Labour Managed Firmsr management (PM) strategies can contribute a great deal to the overall power saving by putting unused components into low-power states and waking them up properly in an intelligent manner. Due to its ease of use and flexibility PW strategies are often implemented in SW. PM strategies are analyzed b作者: 服從 時(shí)間: 2025-3-23 13:02 作者: 擔(dān)憂 時(shí)間: 2025-3-23 16:15
https://doi.org/10.1007/978-1-4615-4251-3need to provide smart functions with a high performance including real-time computing capabilities, connectivity, and remote access as well as safety, security, and high reliability. At the same time they have to be cheap, work efficiently with an extremely small amount of memory and limited resourc作者: HUMID 時(shí)間: 2025-3-23 21:28 作者: 發(fā)酵劑 時(shí)間: 2025-3-23 23:56
Preliminaries,inally, this chapter introduces the main concepts of Coverage-guided Fuzzing (CGF) and symbolic execution. Both are very effective techniques for SW testing and verification and serve as foundation for several verification approaches developed in this book.作者: 搬運(yùn)工 時(shí)間: 2025-3-24 03:13
l verification methods and advanced coverage-guided testing .This book presents a comprehensive set of techniques that enhance all key aspects of a modern Virtual Prototype (VP)-based design flow. The authors emphasize automated formal verification methods, as well as advanced coverage-guided analys作者: 使成整體 時(shí)間: 2025-3-24 08:16
https://doi.org/10.1007/978-3-030-28936-2inally, this chapter introduces the main concepts of Coverage-guided Fuzzing (CGF) and symbolic execution. Both are very effective techniques for SW testing and verification and serve as foundation for several verification approaches developed in this book.作者: 有惡臭 時(shí)間: 2025-3-24 11:04 作者: intelligible 時(shí)間: 2025-3-24 15:17
https://doi.org/10.1057/9780230288843 shared memory communication and event-based synchronization. CGF is applied for verification of Instruction Set Simulators (ISSs), i.e. an abstract model of a processor core, and is further improved by integrating functional coverage and a custom mutation procedure tailored for ISS verification.作者: 字謎游戲 時(shí)間: 2025-3-24 21:00 作者: 顛簸下上 時(shí)間: 2025-3-25 01:06
Coverage-Guided Testing for Scalable Virtual Prototype Verification, shared memory communication and event-based synchronization. CGF is applied for verification of Instruction Set Simulators (ISSs), i.e. an abstract model of a processor core, and is further improved by integrating functional coverage and a custom mutation procedure tailored for ISS verification.作者: 設(shè)施 時(shí)間: 2025-3-25 03:49
Validation of Firmware-Based Power Management using Virtual Prototypes, large testsuite with different application workload characteristics. And second, an automated coverage-guided approach to generate workloads that maximize the coverage with respect to the PM strategies.作者: Saline 時(shí)間: 2025-3-25 10:24
https://doi.org/10.1007/978-3-319-47373-4 has weaknesses, in particular due to the significant manual effort involved for verification and analysis as well as modeling tasks which is both time consuming and error prone. This chapter presents the VP-based design flow in more detail and introduces the main contributions of the book, that strongly enhance the VP-based design flow.作者: eulogize 時(shí)間: 2025-3-25 14:26 作者: Jogging 時(shí)間: 2025-3-25 16:40 作者: 古董 時(shí)間: 2025-3-25 22:48
nstrate their effectiveness in enhancing the VP-based design flow. Furthermore, the book puts a particular focus on the modern RISC-V ISA, with several case-studies covering modeling as well as VP and SW verification aspects..978-3-030-54830-8978-3-030-54828-5作者: cogitate 時(shí)間: 2025-3-26 02:54 作者: jet-lag 時(shí)間: 2025-3-26 05:17
Formal Verification of SystemC-Based Designs using Symbolic Simulation,vides support for verification of cyclic state spaces by preventing revisiting symbolic states and therefore making the verification complete. CSS is a complementary technique that tightly integrates the symbolic simulation engine with the SystemC design under verification to drastically boost the v作者: Spinal-Fusion 時(shí)間: 2025-3-26 11:28
Verification of Embedded Software Binaries using Virtual Prototypes,little effort to integrate peripherals with concolic execution capabilities. The second approach leverages state-of-the-art CGF in combination with VPs to enable a scalable and efficient verification of embedded SW binaries. To guide the fuzzing process the coverage from the embedded SW is combined 作者: DEFT 時(shí)間: 2025-3-26 12:58
Register-Transfer Level Correspondence Analysis, SW against different HW faults. Such an analysis is very important for embedded systems that operate in vulnerable environments or perform safety critical tasks to protect against effects of, for example, radiation and aging.作者: Osmosis 時(shí)間: 2025-3-26 17:58 作者: 龍卷風(fēng) 時(shí)間: 2025-3-26 22:49 作者: 消散 時(shí)間: 2025-3-27 01:47
https://doi.org/10.1057/9780230389694vides support for verification of cyclic state spaces by preventing revisiting symbolic states and therefore making the verification complete. CSS is a complementary technique that tightly integrates the symbolic simulation engine with the SystemC design under verification to drastically boost the v作者: commonsense 時(shí)間: 2025-3-27 06:43
https://doi.org/10.1057/9780230274907little effort to integrate peripherals with concolic execution capabilities. The second approach leverages state-of-the-art CGF in combination with VPs to enable a scalable and efficient verification of embedded SW binaries. To guide the fuzzing process the coverage from the embedded SW is combined 作者: 亞麻制品 時(shí)間: 2025-3-27 11:05 作者: NEEDY 時(shí)間: 2025-3-27 17:28
https://doi.org/10.1007/978-1-4615-4251-3 However, this modern VP-based design flow still has weaknesses, in particular due to the significant manual effort involved for verification and analysis tasks which is both time consuming and error prone. This chapter summarizes the main contributions of the book, that strongly enhance the VP-base作者: 描述 時(shí)間: 2025-3-27 21:27
Introduction,executable abstract model of the entire Hardware (HW) platform and pre-dominantly created in SystemC TLM (Transaction Level Modeling). In contrast to a traditional design flow, which first builds the HW and then the Software (SW), a VP-based design flow enables parallel development of HW and SW by l作者: assail 時(shí)間: 2025-3-27 22:13
Preliminaries,), which is the language of choice to create Virtual Prototypes (VPs). Then, the main concepts of the RISC-V Instruction Set Architecture (ISA) are described. RISC-V is used in several evaluations and case studies in this book and is the ISA implemented in our proposed open-source RISC-V based VP. F作者: 寬容 時(shí)間: 2025-3-28 05:01
An Open-Source RISC-V Evaluation Platform,the RISC-V ecosystem. The VP provides a 32/64 bit RISC-V core with an essential set of peripherals and support for multi-core simulations. In addition, the VP also provides SW debug (through the Eclipse IDE) and coverage measurement capabilities and supports the FreeRTOS, Zephyr and Linux operating 作者: insurrection 時(shí)間: 2025-3-28 08:44 作者: kidney 時(shí)間: 2025-3-28 13:47
Coverage-Guided Testing for Scalable Virtual Prototype Verification,ethods, which may still be susceptible to state space explosion. Compared to the existing simulation-based verification flow this chapter investigates stronger coverage metrics as well as advanced automated test-case generation and refinement techniques. In particular it considers the Data Flow Test作者: 清楚 時(shí)間: 2025-3-28 14:39 作者: 鞠躬 時(shí)間: 2025-3-28 20:34 作者: PURG 時(shí)間: 2025-3-29 00:25
Register-Transfer Level Correspondence Analysis, to utilize information available at different levels of abstraction. The first approach enables an automated TLM-to-RTL property refinement. It enables to transform high-level TLM properties into RTL properties to serve as starting point for RTL property checking. This avoids the manual transformat作者: BROTH 時(shí)間: 2025-3-29 03:26 作者: FLINT 時(shí)間: 2025-3-29 07:40
Maria Luisa Dalla Chiara,Roberto Giuntini,Roberto Leporini,Giuseppe Sergiolilems such as solutions, complex flows, chemical kinetics, Toda lattices and parallel manipulator. .This book is useful to scholars, researchers and advanced technical members of industrial laboratory facilities developing new tools and products..978-1-4899-9090-7978-1-4614-0454-5作者: 無所不知 時(shí)間: 2025-3-29 12:46 作者: 晚來的提名 時(shí)間: 2025-3-29 19:08
Edward Barnabyi?ed due to the occurrence of multiple corporate governance failures which have triggered the introduction or further re?nement of national and inter- tional corporate governance codes. The necessity of regulatory action however rests on the need for a sound understanding of potentially negative e?e作者: indicate 時(shí)間: 2025-3-29 22:20
