標(biāo)題: Titlebook: Embedded Systems: Design, Analysis and Verification; 4th IFIP TC 10 Inter Gunar Schirner,Marcelo G?tz,Franz J. Rammig Conference proceeding [打印本頁] 作者: Addiction 時(shí)間: 2025-3-21 17:13
書目名稱Embedded Systems: Design, Analysis and Verification影響因子(影響力)
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書目名稱Embedded Systems: Design, Analysis and Verification被引頻次
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書目名稱Embedded Systems: Design, Analysis and Verification讀者反饋
書目名稱Embedded Systems: Design, Analysis and Verification讀者反饋學(xué)科排名
作者: 鎮(zhèn)痛劑 時(shí)間: 2025-3-21 22:19
978-3-642-43028-2IFIP International Federation for Information Processing 2013作者: 清唱?jiǎng)?nbsp; 時(shí)間: 2025-3-22 03:09
Embedded Systems: Design, Analysis and Verification978-3-642-38853-8Series ISSN 1868-4238 Series E-ISSN 1868-422X 作者: recession 時(shí)間: 2025-3-22 08:18 作者: accordance 時(shí)間: 2025-3-22 12:24 作者: 蝕刻 時(shí)間: 2025-3-22 15:04 作者: 蝕刻 時(shí)間: 2025-3-22 18:12 作者: 油膏 時(shí)間: 2025-3-22 21:20 作者: 痛苦一生 時(shí)間: 2025-3-23 04:38 作者: 的是兄弟 時(shí)間: 2025-3-23 09:23
,Metrik – Definition und Begriffsabgrenzung,a specification capturing core algorithms. Algorithm development itself largely occurs in Algorithm Design Environments (ADE) with little or no hardware concern. Currently, algorithm and system design environments are disjoint; system level specifications are manually implemented which leads to the 作者: Ophthalmologist 時(shí)間: 2025-3-23 16:37 作者: 人充滿活力 時(shí)間: 2025-3-23 21:15 作者: NEXUS 時(shí)間: 2025-3-24 01:15 作者: cacophony 時(shí)間: 2025-3-24 04:35
https://doi.org/10.1007/978-3-662-32848-4ncerns are arising with an alarming pace. The consequence is an increasing demand of techniques that improve yield as well as lifetime reliability of today’s complex integrated systems. It is requested though, that the solutions result in only minimum penalties on power dissipation and system perfor作者: 模范 時(shí)間: 2025-3-24 06:32 作者: 熒光 時(shí)間: 2025-3-24 11:34 作者: Mawkish 時(shí)間: 2025-3-24 15:07 作者: 上坡 時(shí)間: 2025-3-24 19:29
https://doi.org/10.1007/978-1-4615-0511-2g complexity of application specific instruction-set processors (ASIPs) which are inseparable parts of nowadays complex embedded systems makes this task even more challenging. In ASIPs, it is necessary to test and verify significantly bigger portion of logic, tricky timing behaviour or specific corn作者: evasive 時(shí)間: 2025-3-25 02:12 作者: 種植,培養(yǎng) 時(shí)間: 2025-3-25 03:21 作者: clarify 時(shí)間: 2025-3-25 10:22 作者: AORTA 時(shí)間: 2025-3-25 15:06 作者: stroke 時(shí)間: 2025-3-25 16:34 作者: aplomb 時(shí)間: 2025-3-25 22:53 作者: 安定 時(shí)間: 2025-3-26 01:49
,It’s for Serious Men: Manscaping, multicore platforms this task becomes even more challenging, because of shared processing, communication and memory resources. Model-checking techniques are capable of verifying the performance properties of applications running on these platforms. Unfortunately, these techniques are not scalable w作者: pantomime 時(shí)間: 2025-3-26 04:18 作者: airborne 時(shí)間: 2025-3-26 12:02 作者: Infinitesimal 時(shí)間: 2025-3-26 15:11
https://doi.org/10.1007/978-3-662-40114-9 proposed automatic transformation from SystemC/TLM to . timed automata. With that, we can fully automatically verify memory-related properties of a wide range of practical applications. We show the applicability of our approach by verifying memory safety of an industrial design that makes ample use of pointers and call-by-reference.作者: chastise 時(shí)間: 2025-3-26 20:15 作者: arbiter 時(shí)間: 2025-3-26 21:29 作者: 發(fā)牢騷 時(shí)間: 2025-3-27 04:25 作者: 晚間 時(shí)間: 2025-3-27 06:12 作者: 者變 時(shí)間: 2025-3-27 12:49 作者: Indecisive 時(shí)間: 2025-3-27 15:14
Formal Deadlock Analysis of SpecC Models Using Satisfiability Modulo Theoriesose timing relations. If a conflict is detected, our tool will read the unsatisfiable model generated by the SMT solver and report the cause of the conflict to the user. We demonstrate our approach on a JPEG encoder design model.作者: 有角 時(shí)間: 2025-3-27 19:37 作者: Delirium 時(shí)間: 2025-3-28 02:00 作者: 遵循的規(guī)范 時(shí)間: 2025-3-28 05:21 作者: 發(fā)展 時(shí)間: 2025-3-28 07:36
Jacques Herzog,Pierre de Meuronr in modern cars. First, we investigate relevant ISO standards and legal requirements and derive seven technical requirements for a virtualized automotive HMI system. Based on these requirements, we present the concept for a . that allows for the consolidation of mixed-criticality graphics ECUs.作者: 真實(shí)的你 時(shí)間: 2025-3-28 11:49 作者: mutineer 時(shí)間: 2025-3-28 15:37 作者: FIG 時(shí)間: 2025-3-28 21:17
Automated Functional Verification of Application Specific Instruction-set Processors paper is to introduce an automated generation of SystemVerilog verification environments (testbenches) for verification of ASIPs. Results show that our approach reduces the time and effort needed for implementation of testbenches significantly and is robust enough to detect also well-hidden bugs.作者: Perigee 時(shí)間: 2025-3-28 23:00 作者: 檢查 時(shí)間: 2025-3-29 03:11
Exploiting Segregation in Bus-Based MPSoCs to Improve Scalability of Model-Checking-Based Performancitecture. We will improve the the number of SDFAs being analyzable by our model-checking approach by exploiting the temporal and spatial segregation properties of the TDMA architecture and demonstrate how this method can be applied.作者: 噴出 時(shí)間: 2025-3-29 10:21
1868-4238 TC 10 International Embedded Systems Symposium, IESS 2013, held in Paderborn, Germany, in June 2013. The 22 full revised papers presented together with 8 short papers were carefully reviewed and selected from 42 submissions. The papers have been organized in the following topical sections: design me作者: ALT 時(shí)間: 2025-3-29 14:46
Calibrating scanning probe microscopes,on campaign using an established benchmark suite in the embedded systems domain, we show that the careful selection of the available compiler optimizations is necessary to avoid a significant decrease of software reliability while sustaining the performance boost those optimizations provide.作者: gastritis 時(shí)間: 2025-3-29 17:41 作者: 埋伏 時(shí)間: 2025-3-29 22:41 作者: Pituitary-Gland 時(shí)間: 2025-3-30 01:23 作者: defenses 時(shí)間: 2025-3-30 07:12 作者: Cardiac-Output 時(shí)間: 2025-3-30 11:43 作者: white-matter 時(shí)間: 2025-3-30 16:10 作者: 小教堂 時(shí)間: 2025-3-30 17:04
Improving Education in Desegregated Schools,out decompression, notably for identifying repeated cycles or comparing different cycles. The evaluation demonstrates that our approach reaches high compression ratios on microcontroller execution traces.作者: Dictation 時(shí)間: 2025-3-30 21:48 作者: abolish 時(shí)間: 2025-3-31 03:56 作者: LUMEN 時(shí)間: 2025-3-31 05:38
Programming Robots with Eventsa mechanism to handle various kinds of changes happening in the environment. Event handlers run in parallel either synchronously or asynchronously, and events can be reconfigured at runtime to modify their behavior when needed. We apply INI to the humanoid robot called Nao, for which we develop an o作者: Cardioplegia 時(shí)間: 2025-3-31 09:17
Joint Algorithm Developing and System-Level Design: Case Study on Video Encodinga specification capturing core algorithms. Algorithm development itself largely occurs in Algorithm Design Environments (ADE) with little or no hardware concern. Currently, algorithm and system design environments are disjoint; system level specifications are manually implemented which leads to the 作者: 象形文字 時(shí)間: 2025-3-31 14:48
Automatic Execution of Test Cases on UML Models of Embedded Systemsthe engineers have to identify and fix the introduced errors as soon as possible. Therefore, it makes sense to facilitate the errors detection during the whole the design cycle, including the initial specification stages. This work proposed a test-based approach to aid the early verification of embe作者: legislate 時(shí)間: 2025-3-31 20:56
Compiler Optimizations Do Impact the Reliability of Control-Flow Radiation Hardened Embedded Softwarue to enable the software itself to detect and correct radiation induced soft-errors occurring in branches. Supported by a comprehensive fault injection campaign using an established benchmark suite in the embedded systems domain, we show that the careful selection of the available compiler optimiza作者: 加花粗鄙人 時(shí)間: 2025-3-31 22:35
Power Reduction in Embedded Systems Using a Design Methodology Based on Synchronous Finite State Macs. The proposed Model-Based-Development process uses Synchronous Finite State Machines (SFSM) to model the behavior of low-power devices. This methodology is aimed at devices at the lower-end of the complexity spectrum, as long as the device behavior can be modeled as SFSM. The implementation requir作者: 字謎游戲 時(shí)間: 2025-4-1 05:05
Low-Power Processors Require Effective Memory Partitioningoit banked memories with independent low-leakage retention mode in event-driven applications. The resulting energy saving for a given number of banks is close to the maximum achievable value, since the memory banks access pattern of event-driven applications presents a high temporal locality, leadin作者: 鍍金 時(shí)間: 2025-4-1 09:02 作者: 使混合 時(shí)間: 2025-4-1 11:53 作者: Muffle 時(shí)間: 2025-4-1 15:13 作者: Misnomer 時(shí)間: 2025-4-1 19:09 作者: IDEAS 時(shí)間: 2025-4-2 01:26 作者: Obvious 時(shí)間: 2025-4-2 04:01
Compressing Microcontroller Execution Traces to Assist System Analysisted trace makes the trace analysis extremely difficult and time-consuming. In this paper, by leveraging both cycles and repetitions present in an execution trace, we present an approach which offers a compact and accurate trace compression. This compression may be used during the trace analysis with
