標(biāo)題: Titlebook: Embedded Systems Specification and Design Languages; Selected Contributio Eugenio Villar Book 2008 Springer Science+Business Media B.V. 200 [打印本頁] 作者: hypothyroidism 時(shí)間: 2025-3-21 17:33
書目名稱Embedded Systems Specification and Design Languages影響因子(影響力)
書目名稱Embedded Systems Specification and Design Languages影響因子(影響力)學(xué)科排名
書目名稱Embedded Systems Specification and Design Languages網(wǎng)絡(luò)公開度
書目名稱Embedded Systems Specification and Design Languages網(wǎng)絡(luò)公開度學(xué)科排名
書目名稱Embedded Systems Specification and Design Languages被引頻次
書目名稱Embedded Systems Specification and Design Languages被引頻次學(xué)科排名
書目名稱Embedded Systems Specification and Design Languages年度引用
書目名稱Embedded Systems Specification and Design Languages年度引用學(xué)科排名
書目名稱Embedded Systems Specification and Design Languages讀者反饋
書目名稱Embedded Systems Specification and Design Languages讀者反饋學(xué)科排名
作者: acclimate 時(shí)間: 2025-3-21 21:49
An Integrated SystemC Debugging Environmentin simulating, debugging, and visualizing their SystemC models combining high-level debugging with visualization features. Our work mainly focuses on developing an easy to handle interface which supports debugging and system exploration of SystemC designs.作者: 大酒杯 時(shí)間: 2025-3-22 01:55 作者: 減弱不好 時(shí)間: 2025-3-22 05:52
Mixed-Level Modeling Using Configurable MOS Transistor Models transistor model according to effects and implementing a configurable MOS level-1 transistor model in Verilog-A. Several examples of use will show the reduction in simulation time. The proposed approach can be used with any type of transistor model and is easily integrated in circuit simulators such as SPICE.作者: Confidential 時(shí)間: 2025-3-22 11:33 作者: 我說不重要 時(shí)間: 2025-3-22 16:15 作者: 我說不重要 時(shí)間: 2025-3-22 17:26 作者: 閑蕩 時(shí)間: 2025-3-22 23:39
Asynchronous On-Line Monitoring of Logical and Temporal Assertionsgic which gives reliable and robust monitors in the case of truly asynchronous events, temperature or voltage variations. These monitors are applicable to a wider range of verification tasks such as the communications among globally asynchronous modules or in safe or secure applications.作者: 諄諄教誨 時(shí)間: 2025-3-23 01:28
1876-1100 .Latest research results in Analog, Mixed-Signal, and Hetero.FDL is the most important European and, probably, worldwide forum to present research results, to exchange experiences, and to learn about new trends in the application of specification and design languages and the associated design and mo作者: arsenal 時(shí)間: 2025-3-23 07:30 作者: Abnormal 時(shí)間: 2025-3-23 10:53 作者: WATER 時(shí)間: 2025-3-23 15:56
https://doi.org/10.1007/978-94-017-2256-8of this process, specifically we are looking at automatic UML to SystemC transformation. In this paper we compare UML and SystemC, focusing on communication modeling. We also present mapping rules for automatic SystemC code generation from UML. The mapping has been implemented in our UML to SystemC code generator.作者: peak-flow 時(shí)間: 2025-3-23 21:49
Laudan and the Problems of Progress,he tracing facilities of ASC. This paper also presents a patch of the OSCI SystemC simulator allowing to properly validate ASC models. As relevant examples, two versions of the Octagon interconnect are modeled and verified using the ASC library.作者: cunning 時(shí)間: 2025-3-24 00:49
Deasy Simandjuntak,Michaela Haugevel. In this contribution we review these modelling alternatives in the context of SystemC and with focus on bus models, provide quantitative measurements on major alternatives, and propose a CX modelling level that allows to obtain almost cycle accuracy and a simulation performance significantly above CA models.作者: saturated-fat 時(shí)間: 2025-3-24 03:34
Cost-Effectiveness Studies in Oncology,MSP into the existing VHDL-AMS 1076.1 standard automatically. The pre-processor allows development of models with partial differential equations using currently available simulators. As an example, a VHDL-AMSP description for the sensing element of a MEMS accelerometer is presented, converted to VHDL-AMS 1076.1 and simulated in SystemVision.作者: 修正案 時(shí)間: 2025-3-24 09:12 作者: BATE 時(shí)間: 2025-3-24 13:27
On Construction of Cycle Approximate Bus TLMsevel. In this contribution we review these modelling alternatives in the context of SystemC and with focus on bus models, provide quantitative measurements on major alternatives, and propose a CX modelling level that allows to obtain almost cycle accuracy and a simulation performance significantly above CA models.作者: 總 時(shí)間: 2025-3-24 14:58
An Extension to VHDL-AMS for AMS Systems with Partial Differential EquationsMSP into the existing VHDL-AMS 1076.1 standard automatically. The pre-processor allows development of models with partial differential equations using currently available simulators. As an example, a VHDL-AMSP description for the sensing element of a MEMS accelerometer is presented, converted to VHDL-AMS 1076.1 and simulated in SystemVision.作者: 后來 時(shí)間: 2025-3-24 21:38 作者: 戰(zhàn)役 時(shí)間: 2025-3-24 23:40 作者: fledged 時(shí)間: 2025-3-25 04:07 作者: 女上癮 時(shí)間: 2025-3-25 09:16 作者: Prognosis 時(shí)間: 2025-3-25 13:00
Transactor-Based Formal Verification of Real-Time Embedded Systemse such transactors. According to this technique, transactors are specified in a single formal language, which is capable of capturing timing aspects. The approach is especially targeted to formal verification.作者: 羽飾 時(shí)間: 2025-3-25 17:30 作者: condone 時(shí)間: 2025-3-25 23:35 作者: 滑稽 時(shí)間: 2025-3-26 03:08
UML and SystemC – A Comparison and Mapping Rules for Automatic Code Generationof this process, specifically we are looking at automatic UML to SystemC transformation. In this paper we compare UML and SystemC, focusing on communication modeling. We also present mapping rules for automatic SystemC code generation from UML. The mapping has been implemented in our UML to SystemC code generator.作者: Frequency-Range 時(shí)間: 2025-3-26 07:35 作者: 大包裹 時(shí)間: 2025-3-26 10:11 作者: Addictive 時(shí)間: 2025-3-26 16:03
Vagueness and Alternative Logic,a manually developed testbench is hard to quantify. In this paper, an approach for measuring the quality of SystemC testbenches is presented. The approach is based on dedicated code coverage techniques and identifies all the parts of a SystemC model that have not been tested. Experimental results show the applicability of our methodology.作者: LAPSE 時(shí)間: 2025-3-26 18:17
Methods and Materials for Remote Sensing transistor model according to effects and implementing a configurable MOS level-1 transistor model in Verilog-A. Several examples of use will show the reduction in simulation time. The proposed approach can be used with any type of transistor model and is easily integrated in circuit simulators such as SPICE.作者: Postmenopause 時(shí)間: 2025-3-26 23:11
Applications of Mathematical Modeling,may result in a combinatorial loop, with ill-defined behavior; introduction of delays may introduce races, which have to be controlled. We describe here the abilities of the MARTE time model in this respect.作者: Suppository 時(shí)間: 2025-3-27 02:08 作者: bacteria 時(shí)間: 2025-3-27 08:20
Alex Conconi,Sergio Gusmeroli,Roberto Rattiased on the UML2, a SystemC UML profile for the HW side, and a multi-threaded C UML profile for the SW side, which allows modeling of the system at higher levels of abstraction (from a functional executable level to Register Transfer Level) and supports automatic code-generation/back-annotation from/to UML models.作者: 傲慢物 時(shí)間: 2025-3-27 12:43 作者: 銼屑 時(shí)間: 2025-3-27 17:00
1876-1100 ortant aspects in system modeling and specification, an essential area in Embedded Systems design...The objective of .Specification and Design Languages for Heterogeneous HW/SW Embedded Systems. is to serve as 978-90-481-7834-6978-1-4020-8297-9Series ISSN 1876-1100 Series E-ISSN 1876-1119 作者: cancer 時(shí)間: 2025-3-27 17:45
Book 2008 the original content with additional technical information. The papers cover the most important aspects in system modeling and specification, an essential area in Embedded Systems design...The objective of .Specification and Design Languages for Heterogeneous HW/SW Embedded Systems. is to serve as 作者: MAIZE 時(shí)間: 2025-3-28 00:55
Terry P. Kenakin,H. J. Leightonh will be proposed for future standardization. Some practical aspects, such as the current set of MoCs covered by the methodologies and the compatibility on the installation of their associated libraries are also covered by this chapter. A complete illustrative example is used to show HetSC and Syst作者: 強(qiáng)化 時(shí)間: 2025-3-28 05:36 作者: aggressor 時(shí)間: 2025-3-28 08:34
Embedded Systems Specification and Design LanguagesSelected Contributio作者: Admonish 時(shí)間: 2025-3-28 10:57 作者: 沙文主義 時(shí)間: 2025-3-28 14:50 作者: 共同給與 時(shí)間: 2025-3-28 22:14
How Different Are Esterel and SystemCa rather different origin, we show that the execution/simulation of programs written in these languages consists of many corresponding computation steps. As a consequence, we identify different classes of Esterel programs that can be easily translated to SystemC processes and vice versa. Moreover, w作者: 歡樂中國 時(shí)間: 2025-3-29 01:16
Timed Asynchronous Circuits Modeling and Validation Using SystemCrimitives of ASC rely on SystemC immediate notification. In this paper we present a time model which allows us to properly trace ASC processes activity. This time model is not restricted to ASC and could be used to model asynchronous circuits using a CSP based modeling language. Moreover, this time 作者: 發(fā)源 時(shí)間: 2025-3-29 06:38
On Construction of Cycle Approximate Bus TLMsrate (CA) in this contribution. The choice of a level has an impact on simulation accuracy and performance and makes a level suitable for specific use cases, e.g. virtual prototyping, architectural exploration, and verification. Whereas the untimed and cycle-accurate levels have a relatively precise作者: Lucubrate 時(shí)間: 2025-3-29 08:36 作者: 并置 時(shí)間: 2025-3-29 12:39
An Integrated SystemC Debugging Environments in the support of abstraction levels beyond RTL. But being able to implement complex System-on-Chip (SoC) designs in SystemC raises the necessity of new techniques to support debugging, system exploration, and verification..We present an integrated debugging environment that facilitates designers 作者: Laconic 時(shí)間: 2025-3-29 15:37 作者: 莊嚴(yán) 時(shí)間: 2025-3-29 23:18 作者: 簡略 時(shí)間: 2025-3-30 01:27
Heterogeneous Specification with HetSC and SystemC-AMS: Widening the Support of MoCs in SystemCogies. Their joint usage enables the development of SystemC specifications supporting a wide range of Models of Computation (MoCs). This is becoming more and more necessary for building complete specifications of embedded systems, which are increasingly heterogeneous (they include the software contr作者: 過去分詞 時(shí)間: 2025-3-30 05:28
An Extension to VHDL-AMS for AMS Systems with Partial Differential Equationsuage VHDL-AMSP. An important specific need for such extensions arises from the well known MEMS modelling difficulties where complex digital and analogue electronics interfaces with distributed mechanical systems. The new syntax allows descriptions of new VHDL-AMS objects, such as partial quantities,作者: Virtues 時(shí)間: 2025-3-30 11:36 作者: 周年紀(jì)念日 時(shí)間: 2025-3-30 13:42
Modeling AADL Data Communications with UML MARTEme Model subprofile where semantic issues can be explicitly and formally described. As a full-size exercise we deal here with the modeling of immediate and delayed data communications in AADL. It actually reflects an important issue in RT/E model semantics: a propagation of immediate communications 作者: Chipmunk 時(shí)間: 2025-3-30 19:37
Software Real-Time Resource Modelingts and the constant evolution of Real-Time Embedded (RTE) software requirements. One promised solution is the model driven development (MDD) based on the principle of separating the application description from its platform specific implementation. Nowadays, this is often done through dedicated mode作者: intricacy 時(shí)間: 2025-3-30 23:55
Model Transformations from a Data Parallel Formalism Towards Synchronous Languages descriptions. In this paper, a metamodel and a transformation chain are defined from a high-level modeling framework, Gaspard, for data-parallel systems towards a formalism of synchronous equations. These equations are translated in synchronous data-flow languages, such as Lustre, which provide des作者: 使糾纏 時(shí)間: 2025-3-31 04:40
UML and SystemC – A Comparison and Mapping Rules for Automatic Code Generationtem is modeled using different tools and languages. Transformations between the models are traditionally done manually. We investigate the automation of this process, specifically we are looking at automatic UML to SystemC transformation. In this paper we compare UML and SystemC, focusing on communi作者: evaculate 時(shí)間: 2025-3-31 05:47 作者: bleach 時(shí)間: 2025-3-31 12:52 作者: Mercantile 時(shí)間: 2025-3-31 14:58 作者: PLUMP 時(shí)間: 2025-3-31 19:20 作者: 違反 時(shí)間: 2025-4-1 00:59 作者: 止痛藥 時(shí)間: 2025-4-1 03:28
Eugenio VillarUnique collection of selected papers from FDL’07.Improved version of papers from FDL’07.Latest research results in C/C++ Based System Design.Latest research results in Analog, Mixed-Signal, and Hetero作者: infantile 時(shí)間: 2025-4-1 09:54
Lecture Notes in Electrical Engineeringhttp://image.papertrans.cn/e/image/307960.jpg作者: debble 時(shí)間: 2025-4-1 13:51
Sameer Mahmood Zaheer,Ramachandraiah Gosugn automation. We will show how a property-based formal specification of a cache controller for a MIPS core can be used to automatically generate a functional implementation of that controller and how additional performance information about the complete system can be gained from doing so.作者: 現(xiàn)任者 時(shí)間: 2025-4-1 16:04
A Case-Study in Property-Based Synthesis: Generating a Cache Controller from a Property-Setgn automation. We will show how a property-based formal specification of a cache controller for a MIPS core can be used to automatically generate a functional implementation of that controller and how additional performance information about the complete system can be gained from doing so.作者: 沒血色 時(shí)間: 2025-4-1 21:54
https://doi.org/10.1007/978-1-4020-8297-9C++ programming language; Debugging; Embedded System; Signal; SystemC; Unified Modeling Language (UML); an作者: 暴發(fā)戶 時(shí)間: 2025-4-2 02:20
Britta Timm Knudsen,Mads Krogh,Carsten Stagea rather different origin, we show that the execution/simulation of programs written in these languages consists of many corresponding computation steps. As a consequence, we identify different classes of Esterel programs that can be easily translated to SystemC processes and vice versa. Moreover, w
