標題: Titlebook: Embedded Computer Systems: Architectures, Modeling, and Simulation; 19th International C Dionisios N. Pnevmatikatos,Maxime Pelcat,Matthias [打印本頁] 作者: 撒謊 時間: 2025-3-21 17:14
書目名稱Embedded Computer Systems: Architectures, Modeling, and Simulation影響因子(影響力)
書目名稱Embedded Computer Systems: Architectures, Modeling, and Simulation影響因子(影響力)學科排名
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書目名稱Embedded Computer Systems: Architectures, Modeling, and Simulation網絡公開度學科排名
書目名稱Embedded Computer Systems: Architectures, Modeling, and Simulation被引頻次
書目名稱Embedded Computer Systems: Architectures, Modeling, and Simulation被引頻次學科排名
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書目名稱Embedded Computer Systems: Architectures, Modeling, and Simulation讀者反饋
書目名稱Embedded Computer Systems: Architectures, Modeling, and Simulation讀者反饋學科排名
作者: 禁令 時間: 2025-3-21 22:33 作者: Microgram 時間: 2025-3-22 00:55 作者: 寡頭政治 時間: 2025-3-22 08:21
Efficient Dynamic Device Placement for Deep Neural Network Training on Heterogeneous SystemsN model often requires very intensive computational resources. For edge incremental learning, more energy efficient learning solutions are called for. Heterogeneous computing is more power efficient, and has been increasingly popular for embedded platforms. Therefore, how to deploy training models o作者: 搖晃 時間: 2025-3-22 11:23 作者: 廢止 時間: 2025-3-22 13:28 作者: 廢止 時間: 2025-3-22 20:35
A Latency-Optimized Hash-Based Digital Signature Accelerator for the Tactile Internety and security. Security comprises encryption and data authentication. Digital signatures enable the latter. With the rise of quantum computers, most currently employed digital signature schemes will become unsecure. One promising post-quantum secure algorithm is the eXtended Merkle Signature Scheme作者: Cumbersome 時間: 2025-3-23 00:57
Fault Sensitivity Analysis of Lattice-Based Post-Quantum Cryptographic ComponentsShor’s algorithm is expected in the near-to-medium future. Lattice-based PQC algorithms are among the most promising candidates discussed today, due to their performance and versatility. In this paper, we demonstrate fault sensitivity analysis (FSA) of circuit blocks used in lattice-based cryptograp作者: 出價 時間: 2025-3-23 03:31
Scalable Optimal Greedy Scheduler for Asymmetric Multi-/Many-Core Processorsng asymmetric many-core processors are expected to combine hundreds of cores belonging to different types. However, the accompanying task-to-core mapping schedules are the key to achieving the full potential of such processors. Run-time scheduling on asymmetric processors is a much harder problem to作者: 寬宏大量 時間: 2025-3-23 05:48
Platform-Agnostic Learning-Based Schedulingogeneous-ISA architectures with cores implementing different ISAs. As diversity of execution cores grows, predictive models become of paramount importance for scheduling and resource allocation. In this paper, we investigate the capabilities of performance predictors in a heterogeneous-ISA setting, 作者: Meager 時間: 2025-3-23 11:55
Using Frame Similarity for Low Energy Software-Only IoT Video Recognition, frequently used for this task, fail to explore the intrinsic redundancy present in videos: similarity between sequential frames means that analyzing all frames can be avoided. On top of that, while several hardware solutions for low-energy execution have been proposed, they require extra or dedica作者: 波動 時間: 2025-3-23 17:01 作者: Mnemonics 時間: 2025-3-23 19:35
An Open-Hardware Platform for MPSoC Thermal Modelingneration cooling and thermal management solutions. However, extending existing thermal models, or designing new ones to account for new cooling solutions, requires parameter identification as well as a validation phase to ensure correctness of the results. In this paper, we propose a flexible soluti作者: sacrum 時間: 2025-3-23 22:22
978-3-030-27561-7Springer Nature Switzerland AG 2019作者: glans-penis 時間: 2025-3-24 05:39
Embedded Computer Systems: Architectures, Modeling, and Simulation978-3-030-27562-4Series ISSN 0302-9743 Series E-ISSN 1611-3349 作者: Fibrin 時間: 2025-3-24 10:16
https://doi.org/10.1007/978-3-030-27562-4embedded reconfigurable processors; architecture synthesis from functional languages descriptions; emb作者: decode 時間: 2025-3-24 11:56
Lecture Notes in Computer Sciencehttp://image.papertrans.cn/e/image/307889.jpg作者: 礦石 時間: 2025-3-24 15:57 作者: 想象 時間: 2025-3-24 19:54
Kathleen Juncken,Axel R. Heller architectures. In addition, global coherence spanning across all tiles does not scale well. Therefore, we have proposed a region-based cache coherence (RBCC) approach that enables coherence among a selectable cluster of tiles in accordance with application requirements. In this paper, we present a 作者: maculated 時間: 2025-3-25 01:41 作者: 不發(fā)音 時間: 2025-3-25 04:03
Klinisch-chemische Laborverfahren,N model often requires very intensive computational resources. For edge incremental learning, more energy efficient learning solutions are called for. Heterogeneous computing is more power efficient, and has been increasingly popular for embedded platforms. Therefore, how to deploy training models o作者: INERT 時間: 2025-3-25 11:25 作者: bypass 時間: 2025-3-25 15:43
Anhang: Medizinisch-ethische Richtlinien,ared to a cloud solution. As most edge devices are memory- and compute-constrained, they cannot store and execute a complete Deep Neural Network (DNN). One possible solution is to distribute the DNN across multiple edge devices. For a complete distribution, both fully-connected and feature- and weig作者: gastritis 時間: 2025-3-25 16:33 作者: 細微差別 時間: 2025-3-25 20:17
Medizinische Grundkenntnisse für HeilberufeShor’s algorithm is expected in the near-to-medium future. Lattice-based PQC algorithms are among the most promising candidates discussed today, due to their performance and versatility. In this paper, we demonstrate fault sensitivity analysis (FSA) of circuit blocks used in lattice-based cryptograp作者: 現存 時間: 2025-3-26 03:29
https://doi.org/10.1007/978-3-540-72352-3ng asymmetric many-core processors are expected to combine hundreds of cores belonging to different types. However, the accompanying task-to-core mapping schedules are the key to achieving the full potential of such processors. Run-time scheduling on asymmetric processors is a much harder problem to作者: Dictation 時間: 2025-3-26 07:29
W. Eisenmenger,H.-D. Lippert,U. Wandlogeneous-ISA architectures with cores implementing different ISAs. As diversity of execution cores grows, predictive models become of paramount importance for scheduling and resource allocation. In this paper, we investigate the capabilities of performance predictors in a heterogeneous-ISA setting, 作者: 擔憂 時間: 2025-3-26 09:22
https://doi.org/10.1007/978-3-642-87467-3, frequently used for this task, fail to explore the intrinsic redundancy present in videos: similarity between sequential frames means that analyzing all frames can be avoided. On top of that, while several hardware solutions for low-energy execution have been proposed, they require extra or dedica作者: FLEET 時間: 2025-3-26 15:18
https://doi.org/10.1007/978-3-642-97804-3refore, a powerful and energy demanding processing core with an operating system is needed to achieve high data rates. In communication systems that are placed in a high temperature environment, e.g. electronics close to car engines or in aerospace applications, installation space is limited, temper作者: figure 時間: 2025-3-26 17:16
https://doi.org/10.1007/978-3-322-97049-7neration cooling and thermal management solutions. However, extending existing thermal models, or designing new ones to account for new cooling solutions, requires parameter identification as well as a validation phase to ensure correctness of the results. In this paper, we propose a flexible soluti作者: Instantaneous 時間: 2025-3-27 00:29
Conference proceedings 2019tion, SAMOS 2019, held in Pythagorion, Samos, Greece, in July 2019..The 21 regular papers presented were carefully reviewed and selected from 55 submissions. The papers are organized in topical sections on system design space exploration; deep learning optimization; system security; multi/many-core 作者: Crater 時間: 2025-3-27 02:53 作者: 灰心喪氣 時間: 2025-3-27 07:04
A Latency-Optimized Hash-Based Digital Signature Accelerator for the Tactile Internet (XMSS). It is computationally expensive and thus contradicts low latency requirements. This paper proposes a latency-optimized accelerator for hash-based digital signature processing for the XMSS algorithm. Our architecture improves the latency of signing and verification into the sub-millisecond range.作者: FRAUD 時間: 2025-3-27 10:55
Conference proceedings 2019scheduling; system energy and heat management; many-core communication; and electronic system-level design and verification.?In addition there are 13 papers from three special sessions which were organized on topics of current interest: insights from negative results; machine learning implementations; and European projects..作者: 一起 時間: 2025-3-27 14:44 作者: 細微差別 時間: 2025-3-27 21:50
https://doi.org/10.1007/978-3-642-82339-8heme to index the input set of each convolutional layer to its output value. Our experimental results show that for a YOLOv3-tiny CNN, it is possible to achieve a speedup up?to 3.5. while reducing the energy consumption to 22% of the baseline with an accuracy loss of 7.4%.作者: Champion 時間: 2025-3-27 22:42 作者: Analogy 時間: 2025-3-28 04:33 作者: cancellous-bone 時間: 2025-3-28 07:51
Scalable Optimal Greedy Scheduler for Asymmetric Multi-/Many-Core Processorsoptimal (under certain constraints) for asymmetric processors. The proposed scheduler, called ., improves throughput by 26% and reduces average response time by up?to 45% when compared to the default . scheduler on . asymmetric multi-core.作者: inferno 時間: 2025-3-28 13:40
0302-9743 re are 13 papers from three special sessions which were organized on topics of current interest: insights from negative results; machine learning implementations; and European projects..978-3-030-27561-7978-3-030-27562-4Series ISSN 0302-9743 Series E-ISSN 1611-3349 作者: 仲裁者 時間: 2025-3-28 15:20
Kathleen Juncken,Axel R. HellerPGA for a 64-core system and observed a 57% reduction in BRAM-utilization compared to a global coherence directory for regions with up?to 16 cores. Experiments reveal an application acceleration of up?to 42% compared to a message passing based implementation. We also demonstrate the advantage of RBCC-malloc() compared to standalone RBCC.作者: Alveolar-Bone 時間: 2025-3-28 20:16 作者: 斷斷續(xù)續(xù) 時間: 2025-3-29 01:29
https://doi.org/10.1007/978-3-642-87467-3nneeded operations, and can also be used in low-cost hardware readily available for IoT applications. We obtain up?to 12-80x speedup of CNN execution with software-only modifications that require no network retraining while impacting little on accuracy.作者: 胰臟 時間: 2025-3-29 04:02 作者: ALTER 時間: 2025-3-29 08:31
CoD: Coherence-on-Demand – Runtime Adaptable Working Set Coherence for DSM-Based Manycore ArchitectuPGA for a 64-core system and observed a 57% reduction in BRAM-utilization compared to a global coherence directory for regions with up?to 16 cores. Experiments reveal an application acceleration of up?to 42% compared to a message passing based implementation. We also demonstrate the advantage of RBCC-malloc() compared to standalone RBCC.作者: 膽小鬼 時間: 2025-3-29 12:26 作者: Bombast 時間: 2025-3-29 17:13
Using Frame Similarity for Low Energy Software-Only IoT Video Recognitionnneeded operations, and can also be used in low-cost hardware readily available for IoT applications. We obtain up?to 12-80x speedup of CNN execution with software-only modifications that require no network retraining while impacting little on accuracy.作者: 確定 時間: 2025-3-29 20:08 作者: Acupressure 時間: 2025-3-30 00:50 作者: Adrenaline 時間: 2025-3-30 07:05
Dionisios N. Pnevmatikatos,Maxime Pelcat,Matthias 作者: 商業(yè)上 時間: 2025-3-30 10:02
https://doi.org/10.1007/978-3-658-41736-9eed-Solomon encoder. For this algorithm, an application-specific configuration of a transport-triggered architecture has 37.70x of the performance of a standard 8-bit microcontroller while the silicon area is increased by 4.10x.作者: 詞根詞綴法 時間: 2025-3-30 12:51
