作者: 革新 時間: 2025-3-21 21:57
Hardware synthesis in constructive type theory,s business. According to several researches the remedy is formal synthesis. The work presented in this paper was inspired by the work of F K Hanna [3]. Hanna argues that it is preferable to synthesize the circuits directly by a formal design process. It is then possible to discover major design flaw作者: 披肩 時間: 2025-3-22 03:17 作者: 高貴領(lǐng)導(dǎo) 時間: 2025-3-22 07:11
Generic Specification of Digital Hardware,tal hardware. The paper also describes a technique for creating generic specifications in any language with (at least) the expressive power of higher-order logic. This technique is based on the use of higher-order predicates parameterized by function variables and type variables. We believe that thi作者: atopic 時間: 2025-3-22 09:18
High Level Test Generation via Process Composition,on hierarchical and modular design techniques. Functional and behavioral abstraction and transformational approach to synthesis provide direct evidence to it. The notion of testing however, has not received sufficient attention in specification driven design environment. In this paper we shall intro作者: 賄賂 時間: 2025-3-22 16:43
Towards Truly Delay-Insensitive Circuit Realizations of Process Algebras,f primitive building blocks from which they are constructed or in the wires used to interconnect these blocks. While process algebras are widely recognized to provide a good specification language for delay-insensitive circuits, proposed compilation methods have required the use of delay-sensitive c作者: 賄賂 時間: 2025-3-22 20:09 作者: MINT 時間: 2025-3-23 00:10
Specifying the Micro-program Parallelism for Microprocessors of the Von Neumann style,escription levels. Furthermore, we recommend the use of a functional formalism. In this paper, we first recall the functional semantics defined at the “micro-program” level, level which takes into account the memory/processor information exchanges. Then we characterize some validity conditions requi作者: 高深莫測 時間: 2025-3-23 01:32 作者: GUILE 時間: 2025-3-23 08:36 作者: Redundant 時間: 2025-3-23 10:35 作者: 饑荒 時間: 2025-3-23 16:08 作者: 馬籠頭 時間: 2025-3-23 20:29 作者: 盤旋 時間: 2025-3-24 01:56
Proof-based transformation of formal hardware models,o overcome complexity. In many designs, however, optimisation reorganises hierarchy, even at late stages of a design process. Consequently, the partitions of the implementation structure do not always match the functional units of the specification. Instead of hierarchical modularisation, we therefo作者: 不足的東西 時間: 2025-3-24 04:57
Using the Declarative Language LUSTRE for Circuit Verification, associated clock. This paper explains how the language LUSTRE can be used to describe synchronous digital circuits at different levels of abstraction. Then, it presents the associated verification tool LESAR. This tool automatically proves the correctness of a circuit, i.e. that a circuit implement作者: exophthalmos 時間: 2025-3-24 09:47
Optimising designs by transposition, of rearranging components and their interconnections; second, to provide concise parametric representations of such designs; third, to present simple equations that correspond to correctness-preserving transformations of these parametric representations; and finally, to suggest quantitative measure作者: 史前 時間: 2025-3-24 14:37 作者: Inculcate 時間: 2025-3-24 15:21 作者: 運(yùn)動吧 時間: 2025-3-24 19:27
Marina Bar-Shai M.D., Ph.D.,Ehud Klein M.D.ms not typically considered in software oriented theories. These include architectural constraints in the use of type instances, parallelism in the use of multiple instances, and consolidation of distinct types in a common process. Since we are concerned with the question of incorporating (more) con作者: 郊外 時間: 2025-3-24 23:16
https://doi.org/10.1007/978-1-4899-7522-5tal hardware. The paper also describes a technique for creating generic specifications in any language with (at least) the expressive power of higher-order logic. This technique is based on the use of higher-order predicates parameterized by function variables and type variables. We believe that thi作者: Cytokines 時間: 2025-3-25 04:34 作者: Lament 時間: 2025-3-25 07:37
Funding Universal Service Obligationsf primitive building blocks from which they are constructed or in the wires used to interconnect these blocks. While process algebras are widely recognized to provide a good specification language for delay-insensitive circuits, proposed compilation methods have required the use of delay-sensitive c作者: 苦澀 時間: 2025-3-25 14:21
Michael A. Crew,Paul R. Kleindorferlay-insensitive circuits in terms of voltage-level transitions on wires. The approach appears to have several advantages over traditional state-graph and production-rule based methods. The wealth of algebraic laws makes it possible to specify circuits concisely and facilitates the actual designs. In作者: saphenous-vein 時間: 2025-3-25 15:59
Funding Universal Service Obligationsescription levels. Furthermore, we recommend the use of a functional formalism. In this paper, we first recall the functional semantics defined at the “micro-program” level, level which takes into account the memory/processor information exchanges. Then we characterize some validity conditions requi作者: 從容 時間: 2025-3-25 22:46
Future Directions in Well-Beingis in the programming language ML. We began with a proof of the algorithm presented previously and extended it to a level of detail sufficient for proving the implementation of the system. In the process of developing the proof we clarified many definitions presented in previous accounts of the algo作者: 細(xì)絲 時間: 2025-3-26 03:42
Md. Samiul Islam Borno,Md. Abdur Rahmanof assertions based on Dijkstra [4] and UNITY [3] is then developed to formalise specifications of hardware circuit designs, and to establish their correctness. Both combinational and sequential circuits are taken into account, and both in N-mos and C-mos; the latter turns out to be much simpler.作者: Introvert 時間: 2025-3-26 05:16
Leshan Moodliar,Innocent E. Davidsont, we describe the adder algorithms by functional programs processing streams of binary digits. We explain the design decisions leading to the implementations and relate the efficiency gain to concepts known from the theory of programming language semantics. In particular, we relate the synchronism 作者: Limited 時間: 2025-3-26 11:27 作者: 離開就切除 時間: 2025-3-26 13:53
Md. Samiul Islam Borno,Md. Abdur Rahmanhis paper deals with experiences in applying such a tool, OTTER, to the verification of correctness of combinational logic. Several proof methodologies are here discussed: a rewrite rules and a resolution based approach are compared.作者: gonioscopy 時間: 2025-3-26 18:47 作者: Abnormal 時間: 2025-3-26 21:28 作者: 捕鯨魚叉 時間: 2025-3-27 02:43 作者: 磨碎 時間: 2025-3-27 08:48 作者: NAIVE 時間: 2025-3-27 12:10 作者: CAGE 時間: 2025-3-27 15:34
Leshan Moodliar,Innocent E. Davidsonel Planes archi?tecture which has been previously specified as a synchronous concurrent algorithm and has been manually verified. Our aim is to show that OBJ3 is a viable theorem proving tool for complex synchronous concurrent algorithms.作者: ATP861 時間: 2025-3-27 19:46 作者: 替代品 時間: 2025-3-28 00:58 作者: APRON 時間: 2025-3-28 03:05 作者: 相符 時間: 2025-3-28 09:54
Sampling and Proof: A Half-Case Study,In this paper we give a brief introduction to the whiskies of Scotland and the way they are made, with emphasis on the factors affecting the flavour of the final product. Then we discuss the main regions of whisky production, with tasting notes on six exemplars. The paper is best accompanied by a practical session to verify our observations.作者: FILLY 時間: 2025-3-28 10:32
Ruby algebra,An axiomatic definition of the specification language Ruby, suitable for implementing in a theorem prover, is presented. The implementation of this definition in the Isabelle theorem prover is sketched, and examples of its use are shown.作者: avulsion 時間: 2025-3-28 15:12
https://doi.org/10.1007/978-1-4471-3544-9Digital systems; Formal methods; Hardware; Mathematica; Specification driven design; algebra; algorithms; c作者: 熟練 時間: 2025-3-28 21:54 作者: TOM 時間: 2025-3-29 00:02 作者: Silent-Ischemia 時間: 2025-3-29 04:39 作者: enhance 時間: 2025-3-29 10:02
Verification of Synchronous Concurrent Algorithms Using OBJ3: A Case Study of the Pixel-Planes Archel Planes archi?tecture which has been previously specified as a synchronous concurrent algorithm and has been manually verified. Our aim is to show that OBJ3 is a viable theorem proving tool for complex synchronous concurrent algorithms.作者: 事物的方面 時間: 2025-3-29 13:17
Use of the OTTER theorem prover for the formal verification of hardware,his paper deals with experiences in applying such a tool, OTTER, to the verification of correctness of combinational logic. Several proof methodologies are here discussed: a rewrite rules and a resolution based approach are compared.作者: 叢林 時間: 2025-3-29 16:09 作者: 注射器 時間: 2025-3-29 22:36
Proof-based transformation of formal hardware models,ints on signals and for data conversion. Inserted into generic hardware models, the pseudo-components support modular data refinement of circuit descriptions and constraint propagation..Our methodology has been applied to the formal verification of a complex FIR-filter design using the proof system 作者: 形容詞 時間: 2025-3-29 23:58 作者: Gingivitis 時間: 2025-3-30 07:18 作者: 使絕緣 時間: 2025-3-30 08:32 作者: Cocker 時間: 2025-3-30 14:06
1431-1682 ing circuits using UNilY, a formalism that was developed for reasoning about parallel programs. Aagaard and Leeser use standard mathematical tech- niques to pro978-3-540-19659-4978-1-4471-3544-9Series ISSN 1431-1682 作者: BAIL 時間: 2025-3-30 17:29 作者: nurture 時間: 2025-3-31 00:30 作者: 監(jiān)禁 時間: 2025-3-31 00:52
Generic Specification of Digital Hardware,s technique is a very direct (if not the most direct) way to specify hardware generically. Two examples of generic specification are given in the paper: a resettable counter and the programming level model of a very simple microprocessor.作者: painkillers 時間: 2025-3-31 07:19
Towards Truly Delay-Insensitive Circuit Realizations of Process Algebras,omponents such as “isochronic forks.” The use of such delay-sensitive components can introduce subtle errors; we demonstrate that delay sensitive components are unnecessary, and hence pave the way for compilation of process algebras into truly delay insensitive circuits.作者: 石墨 時間: 2025-3-31 12:15
Specifying the Micro-program Parallelism for Microprocessors of the Von Neumann style,red by the “implicit” or “explicit” parallel execution of two micro-programs. We emphasize that our functional formalism and proof methodology are suitable to express the parallelism encountered during instruction execution, in particular for pipelined micro-processors.作者: extinguish 時間: 2025-3-31 13:43 作者: fibula 時間: 2025-3-31 18:37 作者: 詞根詞綴法 時間: 2025-3-31 23:53
Future Directions in Well-Beingving the implementation of the system. In the process of developing the proof we clarified many definitions presented in previous accounts of the algorithm, and discovered several errors in our implementation. The result is that the designs generated by our implementation can be claimed to be ., since we have proved the correctness of our system.作者: Pulmonary-Veins 時間: 2025-4-1 05:46
Leshan Moodliar,Innocent E. Davidsonntations and relate the efficiency gain to concepts known from the theory of programming language semantics. In particular, we relate the synchronism of digital circuits to the strictness of functions.
