作者: Collected 時(shí)間: 2025-3-21 23:40 作者: 無能力 時(shí)間: 2025-3-22 01:54
Fault injection evaluation of assigned signatures in a RISC processor,djustable) execution time and memory overhead. We have measured those overheads in a PowerPC processor and in a Transputer T805 processor, showing that they are completely adjustable. One interesting conclusion is that the best error coverage of the technique does not correspond to the highest amoun作者: Condyle 時(shí)間: 2025-3-22 06:38 作者: 過濾 時(shí)間: 2025-3-22 12:05 作者: NOMAD 時(shí)間: 2025-3-22 15:40 作者: NOMAD 時(shí)間: 2025-3-22 19:24 作者: Offensive 時(shí)間: 2025-3-22 21:56
Design of dependable hardware: What BIST is most efficient?,s (ALU, two-port RAM, registers, latches, random logic, multiplexer-based shifters). The design characteristics and the results of simulation experiments carried out for this circuit show that the proposed solution offers high quality testing at acceptable BIST implementation costs.作者: laceration 時(shí)間: 2025-3-23 03:16 作者: Lipoprotein 時(shí)間: 2025-3-23 09:34 作者: Fibrillation 時(shí)間: 2025-3-23 11:35 作者: 贊成你 時(shí)間: 2025-3-23 14:44
Dynamics During Spectroscopic Transitionsetection mechanisms are evaluated. In these experiments, the fault model consists of highly improbable residual faults to deliberately force the occurrence of fail silence violations. Despite this worst-case scenario, more than 50% of the presumed undetectable errors were detected by other mechanism作者: 暖昧關(guān)系 時(shí)間: 2025-3-23 21:26 作者: 過于光澤 時(shí)間: 2025-3-23 23:34
Musicalization and Mediatization, giving clear results and hints on which components have most influence on MTTF, which must possibly be redesigned or planned redundantly. The customer‘s special requirements could be taken into account by arbitrarily varying the sets of up- and down-states. The approach is assumed to be applicable作者: CERE 時(shí)間: 2025-3-24 05:28 作者: 冰河期 時(shí)間: 2025-3-24 08:37
Dynamics On and Of Complex Networks IIIs (ALU, two-port RAM, registers, latches, random logic, multiplexer-based shifters). The design characteristics and the results of simulation experiments carried out for this circuit show that the proposed solution offers high quality testing at acceptable BIST implementation costs.作者: Contend 時(shí)間: 2025-3-24 14:17 作者: 勉勵(lì) 時(shí)間: 2025-3-24 15:02 作者: 嫌惡 時(shí)間: 2025-3-24 20:48
Adaptable fault tolerance for distributed process control using exclusively standard components,em software and standard protocols. It offers a quick and low cost solution to provide non-safety critical, technical facilities and plants with continuous service. Thereby a maximum of practicability for the application engineers is achieved. The architecture is composed from well known fault toler作者: 牽索 時(shí)間: 2025-3-24 23:50 作者: AND 時(shí)間: 2025-3-25 06:11
Fault injection evaluation of assigned signatures in a RISC processor,valuation of this technique in a modern reduced instruction set processor (RISC). VASC is applied at the machine instructions level and is the very first assigned signature monitoring technique that allows the user to choose block sizes and checking intervals with complete freedom. This feature allo作者: fatty-acids 時(shí)間: 2025-3-25 10:32
An evaluation of the error detection mechanisms in MARS using software-implemented fault injection, Real-Time System (MARS) is a computer system where the hardware, operating system, and application level error detection mechanisms are designed to ensure the fail silence of nodes with a high probability..The goal of this paper is two-fold: First, the error detection capabilities of the different 作者: 黃油沒有 時(shí)間: 2025-3-25 14:05
Dependability modeling and analysis of complex control systems: An application to railway interlocksoftware. It takes into account all aspects of their interactions (including correlation between the diverse software variants) and of the criticality of the several components. Our approach has been to realise the system model in a structured way. This allows to cope with complexity and to focus, w作者: 為現(xiàn)場(chǎng) 時(shí)間: 2025-3-25 19:11
The effect of interfailure time variability on the software reliability growth modelling,nts, are outlined that cast a doubt on the commonly adopted concept of failures ‘ occurrence as a Poisson (either homogeneous or non-homogeneous) process. On a contrived (but plausible for the software practice) example the consequences of this assumption, in some cases inappropriate for the softwar作者: 純樸 時(shí)間: 2025-3-25 20:13 作者: 承認(rèn) 時(shí)間: 2025-3-26 01:27 作者: 猜忌 時(shí)間: 2025-3-26 05:52
Compiler assisted self-checking of structural integrity using return address hashing,h is embedded into the program using a modified GNU C-compiler. Using the return address register as the state variable of the FSM no data overhead occurs. Employing a Compiler for the embedding of the redundant code into the program permits the exploitation of delay slots and jump optimizations for作者: 主動(dòng) 時(shí)間: 2025-3-26 09:58
Single source fault-tolerant broadcasting for two-dimensional meshes without virtual channels,r status information to dynamically construct a broadcast spanning tree when up to .?1 faults are present in an .×. two-dimensional mesh. Correctness proofs for the proposed broadcasting algorithm are presented and the algorithm is also proven to be livelock- and deadlock-free. The proposed Virtual 作者: Flatter 時(shí)間: 2025-3-26 13:07 作者: CARE 時(shí)間: 2025-3-26 20:30 作者: 開頭 時(shí)間: 2025-3-26 21:29
On the yield of VLSI processors with on-chip CPU cache,p VLSI processors with a partially good on-chip cache. Also, we investigate how the yield enhancement of VLSI processors with on-chip CPU cache relates with the number of acceptable faulty cache blocks, the percentage of the cache area with respect to the whole chip area and various manufacturing pr作者: 傲慢人 時(shí)間: 2025-3-27 03:43 作者: 爆米花 時(shí)間: 2025-3-27 08:32 作者: 松軟 時(shí)間: 2025-3-27 11:32
Dynamic testing from bounded data type specifications,which are difficult to find out. As soon as boundaries are clearly identified in a specification, functional testing should be able to address any boundary fault..We propose to enrich a data type specification formalism, namely algebraic specifications, allowing a natural description of data type bo作者: esculent 時(shí)間: 2025-3-27 15:21 作者: 江湖郎中 時(shí)間: 2025-3-27 19:53
Friends: A flexible architecture for implementing fault tolerant and secure distributed applicationded by the sub-systems. Metaobjects are implemented using object-oriented techniques and can be reused and customised according to the application needs, the operational environment and its related fault assumptions. Flexibility is increased by a recursive use of metaobjects. Examples and experiments are also described.作者: MEAN 時(shí)間: 2025-3-27 23:10 作者: FLOAT 時(shí)間: 2025-3-28 04:33 作者: 別名 時(shí)間: 2025-3-28 08:37
On-line testing of an off-the-shelf microprocessor board for safety-critical applications, a minimum impact on the normal behavior of the whole system. Implementation of the described techniques will significantly improve the system ability to safely react to possible faults. This will be quantitatively determined in the subsequent dependability evaluation phase.作者: Munificent 時(shí)間: 2025-3-28 12:07 作者: 浪費(fèi)時(shí)間 時(shí)間: 2025-3-28 16:57 作者: 闖入 時(shí)間: 2025-3-28 22:24 作者: 不舒服 時(shí)間: 2025-3-28 23:07
0302-9743 anized in sections on distributed fault tolerance, fault injection, modelling and evaluation, fault-tolerant design, basic hardware models, testing, verification, replication and distribution, and system level diagnosis.978-3-540-61772-3978-3-540-70677-9Series ISSN 0302-9743 Series E-ISSN 1611-3349 作者: 無意 時(shí)間: 2025-3-29 03:32 作者: 熱心助人 時(shí)間: 2025-3-29 08:00
https://doi.org/10.1007/978-3-319-62983-4 modern RISC processors. The method is evaluated on a SPARC processor using software-implemented control-flow error injection and the SPECint92 benchmark suite. The average temporal overhead is below 20% and the errors violating the fail-silent model can be reduced by a factor of 6 down to 0.3%.作者: Ferritin 時(shí)間: 2025-3-29 13:57
Conference proceedings 19966..The book presents 26 revised full papers selected from a total of 66 submissions based on the reviews of 146 referees. The papers are organized in sections on distributed fault tolerance, fault injection, modelling and evaluation, fault-tolerant design, basic hardware models, testing, verificatio作者: 青石板 時(shí)間: 2025-3-29 15:37
Dynamics in Online Social Networkse the benefit of our approach: an assisted test selection process, formally defined in a functional testing theory, allowing adequate coverage of both data types bounds and the definition domain of the specified operations.作者: 載貨清單 時(shí)間: 2025-3-29 22:43 作者: amenity 時(shí)間: 2025-3-29 23:59 作者: 只有 時(shí)間: 2025-3-30 04:39
On the Routability of the Internetrocedure, and give techniques to select a finite and pertinent test set from an exhaustive test set, including all the possible behaviors of the class under test, by applying test reduction hypothesis. We also study the construction of an oracle, the procedure that analyses the results of the tests, adapted to object-oriented software.作者: 粗俗人 時(shí)間: 2025-3-30 08:45 作者: Graphite 時(shí)間: 2025-3-30 12:36
A theory of specification-based testing for object-oriented software,rocedure, and give techniques to select a finite and pertinent test set from an exhaustive test set, including all the possible behaviors of the class under test, by applying test reduction hypothesis. We also study the construction of an oracle, the procedure that analyses the results of the tests, adapted to object-oriented software.作者: 尊重 時(shí)間: 2025-3-30 17:46
0302-9743 ctober 1996..The book presents 26 revised full papers selected from a total of 66 submissions based on the reviews of 146 referees. The papers are organized in sections on distributed fault tolerance, fault injection, modelling and evaluation, fault-tolerant design, basic hardware models, testing, v作者: 鍍金 時(shí)間: 2025-3-30 22:45 作者: 粉筆 時(shí)間: 2025-3-31 04:01
Efficiency of Navigation in Indexed Networks a minimum impact on the normal behavior of the whole system. Implementation of the described techniques will significantly improve the system ability to safely react to possible faults. This will be quantitatively determined in the subsequent dependability evaluation phase.作者: 違法事實(shí) 時(shí)間: 2025-3-31 07:53
Network-Based Models in Molecular Biology to determine if a bridging fault with local feedback gives an intermediate voltage which is higher or lower than a given threshold voltage. The approach is extremely faster than the previous ones since no SPICE simulation is required.作者: 似少年 時(shí)間: 2025-3-31 11:31
Advances in the Theory of Complex Networkss with the number of acceptable faulty cache blocks, the percentage of the cache area with respect to the whole chip area and various manufacturing process parameters as defect densities and the fault clustering parameter.作者: 不遵守 時(shí)間: 2025-3-31 14:57
Reporting and Business Analysis,ms and libraries of metaobjects. Transparency and separation of concerns is provided not only to the application programmer but also to the programmers implementing metaobjects for fault tolerance, secure communication and distribution. Common services required for implementing metaobjects are provi作者: correspondent 時(shí)間: 2025-3-31 20:10 作者: Munificent 時(shí)間: 2025-3-31 22:28
Configuration and Post-Installation, faultinjection experiments. In an earlier paper, several techniques for sampling the fault/activity input space of a fault tolerance mechanism were presented. Various estimators based on simple sampling in the whole space and stratified sampling in a partitioned space were studied; confidence limit作者: Bumble 時(shí)間: 2025-4-1 05:51 作者: 悄悄移動(dòng) 時(shí)間: 2025-4-1 06:43
Dynamics During Spectroscopic Transitions Real-Time System (MARS) is a computer system where the hardware, operating system, and application level error detection mechanisms are designed to ensure the fail silence of nodes with a high probability..The goal of this paper is two-fold: First, the error detection capabilities of the different