標(biāo)題: Titlebook: Defect and Fault Tolerance in VLSI Systems; Volume 2 C. H. Stapper,V. K. Jain,G. Saucier Book 1990 Springer Science+Business Media New York [打印本頁] 作者: Novice 時(shí)間: 2025-3-21 17:13
書目名稱Defect and Fault Tolerance in VLSI Systems影響因子(影響力)
書目名稱Defect and Fault Tolerance in VLSI Systems影響因子(影響力)學(xué)科排名
書目名稱Defect and Fault Tolerance in VLSI Systems網(wǎng)絡(luò)公開度
書目名稱Defect and Fault Tolerance in VLSI Systems網(wǎng)絡(luò)公開度學(xué)科排名
書目名稱Defect and Fault Tolerance in VLSI Systems被引頻次
書目名稱Defect and Fault Tolerance in VLSI Systems被引頻次學(xué)科排名
書目名稱Defect and Fault Tolerance in VLSI Systems年度引用
書目名稱Defect and Fault Tolerance in VLSI Systems年度引用學(xué)科排名
書目名稱Defect and Fault Tolerance in VLSI Systems讀者反饋
書目名稱Defect and Fault Tolerance in VLSI Systems讀者反饋學(xué)科排名
作者: 完成 時(shí)間: 2025-3-22 00:03 作者: 意見一致 時(shí)間: 2025-3-22 02:32 作者: Afflict 時(shí)間: 2025-3-22 05:33 作者: Dendritic-Cells 時(shí)間: 2025-3-22 09:32 作者: 江湖郎中 時(shí)間: 2025-3-22 15:28 作者: 江湖郎中 時(shí)間: 2025-3-22 19:23 作者: PLIC 時(shí)間: 2025-3-23 00:26 作者: HAIL 時(shí)間: 2025-3-23 05:00
CRT-Pacing Only Versus CRT-DefibrillatorA large number of reconfiguration schemes have been presented for defect tolerant mesh arrays. Here a number of such schemes will be compared. Area and speed based measures are presented, along with a summary of the methods required to estimate area overhead, processor utilization, yield and speed.作者: kindred 時(shí)間: 2025-3-23 06:28
The Effect on Yield of Clustering and Radial Variations in Defect DensityThis work examines the effect on yield, of the clustering and radial variation of fatal defects. An expression is developed for fatal defects as a function of chip area and distance of the chip from the edge of the wafer, and used to estimate the yield of successively larger numbers of array segments of a bipolar SRAM.作者: 獸群 時(shí)間: 2025-3-23 10:14 作者: 容易做 時(shí)間: 2025-3-23 16:47 作者: Engaged 時(shí)間: 2025-3-23 19:00 作者: 偽造 時(shí)間: 2025-3-24 01:58 作者: 浮夸 時(shí)間: 2025-3-24 03:05 作者: 小卷發(fā) 時(shí)間: 2025-3-24 07:04 作者: 有罪 時(shí)間: 2025-3-24 14:01
https://doi.org/10.1007/978-981-13-0782-9ith spare rows and columns. By studying the probability of successful application of these heuristics, we are able to make statements about their average performance. Finally, an algorithm which almost always runs in polynomial time based on an appropriate failure rate is presented.作者: antenna 時(shí)間: 2025-3-24 18:28
State of Research on Devotional Fitnesses rapidly as their size decreases, not only because of the larger number of small airborne particulates but also because of the particulates from tools and semiconductor materials. Even with better clean rooms, this larger defect density can cause drastic yield reductions unless specific measures are taken to reduce its impact.作者: 座右銘 時(shí)間: 2025-3-24 20:22 作者: 粗野 時(shí)間: 2025-3-24 23:08 作者: parasite 時(shí)間: 2025-3-25 06:16 作者: Flinch 時(shí)間: 2025-3-25 10:07 作者: 花費(fèi) 時(shí)間: 2025-3-25 11:51 作者: ear-canal 時(shí)間: 2025-3-25 18:16
N.G. Stocks,A. Nikitin,R.P. MorseConsequently, models for yield analysis have been proposed for “l(fā)arge area clustering” and “small area clustering”. By adding a new parameter, the ., to the existing parameters of the defect distribution we unify the analysis of the existing models and at the same time add a whole range of “medium s作者: 危險(xiǎn) 時(shí)間: 2025-3-25 20:43
Preliminaries: Basics and Notation,irectly from the circuit layout provide yield estimates for each circuit piece. Such simulations predict that random point defects will cause less than 1% of the 1266-transistor switches to fail. Yield estimates for each circuit piece are used as inputs to a yield model to evaluate the fault toleran作者: 移動(dòng) 時(shí)間: 2025-3-26 03:38
Carsten Timmermann,Julie Anderson-out-of-n, k < n, unit group, called a block, is operated with k units being worked in the normal operation and the remaining (n-k) units being used as spares. The n switching parts in the block, instead of the traditional k ones, can also mask the faults in the switching part of the block. Under th作者: FLIRT 時(shí)間: 2025-3-26 08:22
Takahiro Ueyama,Christophe Lécuyerrchitectures are often used in highly dependable systems. However, these architectures have several drawbacks for onboard equipments: cost, weight, volume, power consumption and dissipation often lead to difficult problems. In other respects, if duplex architectures allow to reduce some of these pro作者: BRUNT 時(shí)間: 2025-3-26 09:01
Devices for Cardiac Resynchronization: to prevent a consistent reduction of the production yield and a short functioning life of devices. These problems become particularly important when the application is critical and maintenance is difficult or impossible. In the APES environment some tools are available to evaluate statistically the作者: 作繭自縛 時(shí)間: 2025-3-26 13:46
https://doi.org/10.1007/978-981-13-0782-9 reconfigurable chips in which there are redundant elements that can be used to replace the defective elements. The fault covering problem is to assign redundant elements to replace the defective elements such that the chip will function properly. A general formulation to represent the relationship 作者: Alopecia-Areata 時(shí)間: 2025-3-26 17:35
https://doi.org/10.1007/978-981-13-0782-9ith spare rows and columns. By studying the probability of successful application of these heuristics, we are able to make statements about their average performance. Finally, an algorithm which almost always runs in polynomial time based on an appropriate failure rate is presented.作者: Insensate 時(shí)間: 2025-3-27 00:14 作者: Anthrp 時(shí)間: 2025-3-27 04:58 作者: 安撫 時(shí)間: 2025-3-27 05:16 作者: 羞辱 時(shí)間: 2025-3-27 09:47
https://doi.org/10.1007/978-3-319-49823-2ontrol are solved in a natural way by energy efficient and robust neural systems. Hopfield in his seminal paper [1] on physical systems with emergent computational abilities envisioned a new breed of integrated circuits that could implement such systems and would be much less sensitive to element fa作者: neuron 時(shí)間: 2025-3-27 14:49
Yield Models - Comparative Studyabilities. This situation is due, among other things, to the fact that yield models are very often evaluated by using very different, and not always explicitly defined, evaluation criteria. The goal of this paper is to indicate a number of simple yield model characteristics which could be used to improve comparison of different yield models.作者: 門閂 時(shí)間: 2025-3-27 21:41
Extended Duplex Fault Tolerant System With Integrated Control Flow Checkinglume, power consumption and dissipation often lead to difficult problems. In other respects, if duplex architectures allow to reduce some of these problems, they do not provide the same availability characteristics.作者: Tidious 時(shí)間: 2025-3-28 01:29 作者: 離開可分裂 時(shí)間: 2025-3-28 02:08
Reliability Analysis of Application-Specific Architectureso failure due to metal electromigration will be diminished by a factor of α. [1]. In addition, an increase in clock rate requires that nodes be charged and discharged more rapidly, increasing the switching current in some technologies.作者: DAMN 時(shí)間: 2025-3-28 07:41
Fault Tolerance in Analog VLSI: Case Study of a Focal Plane Processorcomputational abilities envisioned a new breed of integrated circuits that could implement such systems and would be much less sensitive to element failure than present day computers. Analog VLSI is a technology suitable for the implementation of synthetic neural systems [2, 3] on silicon.作者: NAUT 時(shí)間: 2025-3-28 14:12 作者: 微生物 時(shí)間: 2025-3-28 18:03 作者: Peristalsis 時(shí)間: 2025-3-28 20:26
A Unified Approach to Yield Analysis of Defect Tolerant Circuitsize clustering” models, thus increasing the flexibility in choosing the appropriate yield model. We illustrate our approach through several numerical examples and propose methods for estimating the newly defined block size.作者: glisten 時(shí)間: 2025-3-28 23:01
Carsten Timmermann,Julie Andersoncessor with redundancy structure is implemented by 2.4 times hardware amount compared to the nonredundancy one, and the proposed structure can improve yield of the chip to any good value by increasing the number of blocks. This paper also proposes a new implementation method of automatic reconfiguration of this network using hardware permuter.作者: Cabinet 時(shí)間: 2025-3-29 06:59
https://doi.org/10.1007/978-3-319-49823-2ies of matrix operations [7], [8]. The methods encode data at a high level, and algorithms are designed to operate on encoded data and produce encoded i. e. corrected output data. However the approach has to be “customized” any time it is applied to a specific algorithm.作者: 真實(shí)的你 時(shí)間: 2025-3-29 10:57 作者: 座右銘 時(shí)間: 2025-3-29 14:30
Arithmetic-Based Diagnosis in VLSI Array Processorsies of matrix operations [7], [8]. The methods encode data at a high level, and algorithms are designed to operate on encoded data and produce encoded i. e. corrected output data. However the approach has to be “customized” any time it is applied to a specific algorithm.作者: hemoglobin 時(shí)間: 2025-3-29 17:24
the need to incorporate defect-tolerance and fault-tolerance in the design of VLSI and WSI systems. The goals of defect-tolerance and fault-tolerance are yield enhancement and improved reliahility. The emphasis on this area has resulted in a new field of interdisciplinary scientific research. I n f作者: 貿(mào)易 時(shí)間: 2025-3-29 20:41
Device Applications of Nonlinear Dynamicsabilities. This situation is due, among other things, to the fact that yield models are very often evaluated by using very different, and not always explicitly defined, evaluation criteria. The goal of this paper is to indicate a number of simple yield model characteristics which could be used to improve comparison of different yield models.作者: Transfusion 時(shí)間: 2025-3-29 23:56 作者: fiscal 時(shí)間: 2025-3-30 07:17 作者: 腐敗 時(shí)間: 2025-3-30 11:36 作者: PACK 時(shí)間: 2025-3-30 14:30
https://doi.org/10.1007/978-3-319-49823-2computational abilities envisioned a new breed of integrated circuits that could implement such systems and would be much less sensitive to element failure than present day computers. Analog VLSI is a technology suitable for the implementation of synthetic neural systems [2, 3] on silicon.作者: GRILL 時(shí)間: 2025-3-30 17:08 作者: 模范 時(shí)間: 2025-3-30 22:30 作者: Intend 時(shí)間: 2025-3-31 01:24
A Unified Approach to Yield Analysis of Defect Tolerant CircuitsConsequently, models for yield analysis have been proposed for “l(fā)arge area clustering” and “small area clustering”. By adding a new parameter, the ., to the existing parameters of the defect distribution we unify the analysis of the existing models and at the same time add a whole range of “medium s作者: 訓(xùn)誡 時(shí)間: 2025-3-31 09:00 作者: 發(fā)炎 時(shí)間: 2025-3-31 09:55
Fault-Tolerant k-out-of-n Logic Unit Network with Minimum Interconnection-out-of-n, k < n, unit group, called a block, is operated with k units being worked in the normal operation and the remaining (n-k) units being used as spares. The n switching parts in the block, instead of the traditional k ones, can also mask the faults in the switching part of the block. Under th作者: GROWL 時(shí)間: 2025-3-31 16:34
Extended Duplex Fault Tolerant System With Integrated Control Flow Checkingrchitectures are often used in highly dependable systems. However, these architectures have several drawbacks for onboard equipments: cost, weight, volume, power consumption and dissipation often lead to difficult problems. In other respects, if duplex architectures allow to reduce some of these pro作者: 高歌 時(shí)間: 2025-3-31 19:18 作者: 可憎 時(shí)間: 2025-3-31 22:35
An Integer Linear Programming Approach to General Fault Covering Problems reconfigurable chips in which there are redundant elements that can be used to replace the defective elements. The fault covering problem is to assign redundant elements to replace the defective elements such that the chip will function properly. A general formulation to represent the relationship 作者: lipids 時(shí)間: 2025-4-1 05:12
Probabilistic Analysis of Memory Repair and Reconfiguration Heuristicsith spare rows and columns. By studying the probability of successful application of these heuristics, we are able to make statements about their average performance. Finally, an algorithm which almost always runs in polynomial time based on an appropriate failure rate is presented.作者: 發(fā)牢騷 時(shí)間: 2025-4-1 08:07
Arithmetic-Based Diagnosis in VLSI Array Processorseasy-testable techniques allow an array to be modified in such a way that the testing time is independent of the array size [1] – [4]. This approach exploits the structural properties of iterative arrays which are modeled as combinational circuits. Different testability conditions have been establis作者: 土產(chǎn) 時(shí)間: 2025-4-1 10:41
Yield Improvement Through X-RAY Lithographyes rapidly as their size decreases, not only because of the larger number of small airborne particulates but also because of the particulates from tools and semiconductor materials. Even with better clean rooms, this larger defect density can cause drastic yield reductions unless specific measures a作者: 火光在搖曳 時(shí)間: 2025-4-1 17:40
Reliability Analysis of Application-Specific Architecturesmportant issue. For example, empirical studies have shown that as a technology undergoes constant-current scaling by a factor of α., the median time to failure due to metal electromigration will be diminished by a factor of α. [1]. In addition, an increase in clock rate requires that nodes be charge作者: 痛恨 時(shí)間: 2025-4-1 19:41 作者: charisma 時(shí)間: 2025-4-2 00:57
An Integer Linear Programming Approach to General Fault Covering Problemstion problem for which there are known methods of solution. To demonstrate the effectiveness of the integer linear programming approach, we studied three different fault covering problems, namely, the fault covering problems for redundant RAMs, the fault covering problems for arrays of RAMs with sha作者: 正論 時(shí)間: 2025-4-2 03:52
Systematic Extraction of Critical Areas From IC Layouts...., ..作者: 易于 時(shí)間: 2025-4-2 09:38 作者: 愚笨 時(shí)間: 2025-4-2 14:27
on- tinued. preferahly on a yearly hasis. It was Dr. I. Koren who organized the "IEEE Inter national Workshop on Defect and Fault Tolerance in VLSI Systems" in Springfield Massachusetts the next year. Selected papers from that workshop were puhlished as the first volume of this series [21.978-1-4757-9959-0978-1-4757-9957-6作者: 慢跑 時(shí)間: 2025-4-2 18:52
https://doi.org/10.1007/978-981-13-0782-9tion problem for which there are known methods of solution. To demonstrate the effectiveness of the integer linear programming approach, we studied three different fault covering problems, namely, the fault covering problems for redundant RAMs, the fault covering problems for arrays of RAMs with sha作者: 傷心 時(shí)間: 2025-4-2 21:21
