書目名稱Correct Hardware Design and Verification Methods影響因子(影響力)學科排名
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書目名稱Correct Hardware Design and Verification Methods網(wǎng)絡公開度學科排名
書目名稱Correct Hardware Design and Verification Methods被引頻次
書目名稱Correct Hardware Design and Verification Methods被引頻次學科排名
書目名稱Correct Hardware Design and Verification Methods年度引用
書目名稱Correct Hardware Design and Verification Methods年度引用學科排名
書目名稱Correct Hardware Design and Verification Methods讀者反饋
書目名稱Correct Hardware Design and Verification Methods讀者反饋學科排名
作者: 耐寒 時間: 2025-3-21 21:59 作者: 語言學 時間: 2025-3-22 01:50 作者: 戲服 時間: 2025-3-22 07:19 作者: 良心 時間: 2025-3-22 09:45
Conference proceedings 1999are now migrating into industrial use. The aim of CHARME’99 is to bring together researchers and users from academia and industry working in this active area of research. Two invited talks illustrate major current trends: the presentation by G′erard Berry (Ecole des Mines de Paris, Sophia-Antipolis,作者: debble 時間: 2025-3-22 14:36
Vacuity Detection in Temporal Model Checkingr the satisfaction of specifications..For example, verifying a system with respect to the specification ? = AG(req → AFgrant) (“every request is eventually followed by a grant”), we say that ? is satisfied vacuously in systems in which requests are never sent. An interesting witness for the satisfac作者: debble 時間: 2025-3-22 18:24
Efficient Verification of Timed Automata Using Dense and Discrete Time Semanticsmmunication between two synchronous systems. Using discrete time and BDDs we were able to prove correctness of a STARI implementation with 18 stages (55 clocks), better than what has been achieved using other techniques. The verification results carry over to the dense semantics..Using variable-dime作者: THROB 時間: 2025-3-22 21:41
From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checkinglways intractably large, of size exponential in the number of bits in the state space. In contrast, under the assumption of full symmetry, we show that it is possible to reduce a textual program description of a symmetric system to a textual program description of the symmetry reduced system. This o作者: cloture 時間: 2025-3-23 04:29 作者: 辭職 時間: 2025-3-23 08:26
0302-9743 academia and industry working in this active area of research. Two invited talks illustrate major current trends: the presentation by G′erard Berry (Ecole des Mines de Paris, Sophia-Antipolis,978-3-540-66559-5978-3-540-48153-9Series ISSN 0302-9743 Series E-ISSN 1611-3349 作者: obscurity 時間: 2025-3-23 12:10
Esterel and Jazz : Two Synchronous Languages for Circuit Designgrams are imperative, concurrent, and preemption based. Programs are translated into circuits that are optimized using specific sequential optimization algorithms. A verification system restricted to the pure control part of programs is available. Esterel is currently used by several CAD vendors and作者: hypotension 時間: 2025-3-23 17:42
Design Process of Embedded Automotive Systems—Using Model Checking for Correct Specificationsn processes can not cope with this complexity. In the first part of this paper we show the current development-process at BMW, the second part deals with our results of using model checking to verify .-models.作者: 吝嗇性 時間: 2025-3-23 21:52 作者: 積習已深 時間: 2025-3-24 00:02
Formal Verification of Explicitly Parallel Microprocessorsmemory access,or multimedia instructions—that allow the compiler or programmer to express more instruction-level parallelism than the microarchitecture is willing to derive. In this paper we show how these instruction-set extensions can be put to use when formally verifying the correctness of a micr作者: Forage飼料 時間: 2025-3-24 05:03
Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpsuper- scalar processors. We achieve a significant speedup in the verification of such processors, compared to the result by Burch [.], while using an entirely automatic tool. Instrumental to our success are exploiting the properties of positive equality [.][.] and the simplification capabilities of作者: arousal 時間: 2025-3-24 08:51 作者: 吞沒 時間: 2025-3-24 10:43
Efficient Decompositional Model Checking for Regular Timing Diagramsnotation is often more convenient than the use of temporal logic or automata. We introduce a class of timing diagrams called .. RTD’s have a precise syntax, and a formal semantics that is simple and corresponds to common usage. Moreover, RTD’s have an inherent compositional structure, which is explo作者: 半球 時間: 2025-3-24 15:11 作者: 相符 時間: 2025-3-24 22:43
Using Symbolic Model Checking to Verify the Railway Stations of Hoorn-Kersenboogerd and Heerhugowaar [.] that the method has potential to increase the capacity of formal verification tools for hardware.In this paper,we examine this potential in light of an experiment in the opposite direction: the application of symbolic model checking to railway interlocking software previously verified with St?l作者: 遷移 時間: 2025-3-25 02:18 作者: nullify 時間: 2025-3-25 05:52
Efficient Verification of Timed Automata Using Dense and Discrete Time Semanticsion. Contrary to some misconceptions, the discrete semantics is not inherently bound to use state-explosive techniques any more than the dense one. In fact, discrete timed automata can be analyzed using any representation scheme (such as DBM) used for dense time, and in addition can benefit from enu作者: 令人發(fā)膩 時間: 2025-3-25 10:01
From Asymmetry to Full Symmetry: New Techniques for Symmetry Reduction in Model Checkingric. We formalize several notions of near symmetry and show how to obtain the benefits of symmetry reduction when applied to asymmetric systems which are nearly symmetric. We show that for some nearly symmetric systems it is possible to perform symmetry reduction and obtain a bisimilar (up to permut作者: 影響 時間: 2025-3-25 14:37
Automatic Error Correction of Large Circuits Using Boolean Decomposition and Abstraction and industry. In this paper, we present a method for localizing and correcting errors in combinatorial circuits for which equivalence checking has failed. Our approach is general and does not assume any error model. Thus, it allows the detection of arbitrary design errors. Since our method is . str作者: 疼死我了 時間: 2025-3-25 18:42
Abstract BDDs: A Technique for Using Abstraction in Model Checkingstructure. We show that this technique builds a more refined model than traditional compiler-based methods proposed by Clarke, Grumberg and Long. We also provide experimental results to demonstrate the usefulness of our method. We have verified a pipelined carry-save multiplier and a simple version 作者: interlude 時間: 2025-3-25 21:23 作者: 決定性 時間: 2025-3-26 01:56 作者: 受傷 時間: 2025-3-26 04:21 作者: 慢跑 時間: 2025-3-26 10:27
Formal Verification of Designs with Complex Control by Symbolic Simulationication tool combines symbolic simulation with a hierarchy of equivalence checking methods, including decision-diagram based techniques, with increasing accuracy in order to optimize overall verification time without giving false negatives. The equivalence checker is able to cope with different numb作者: Pastry 時間: 2025-3-26 16:04
Hints to Accelerate Symbolic Traversalrevents its application to large designs. The lack of flexibility of the conventional breadth-first approach to state search is often responsible for the excessive growth of the BDDs. In this paper we show that the use of . to guide the exploration of the state space may result in orders-of-magnitud作者: debunk 時間: 2025-3-26 19:04
0302-9743 e formal techniques and tools for the design and veri?cation of hardware and systems. Previous conferences have been held in Darmstadt (1984), Edinburgh (1985), Grenoble (1986), Glasgow (1988), Leuven (1989), Torino (1991), Arles (1993), Frankfurt (1995) and Montreal (1997). This workshop and confer作者: agnostic 時間: 2025-3-26 23:43
Conflict, Commitment and Well-Being,cepts a subclass of TLA. specifications that should include most descriptions of real system designs. It has been used by engineers to find errors in the cache coherence protocol for a new Compaq multiprocessor. We describe TLA. specifications and their TLC models, how TLC works, and our experience using it.作者: Suggestions 時間: 2025-3-27 02:35 作者: 捕鯨魚叉 時間: 2025-3-27 06:16
Jozef Baruník,Ev?en Ko?enda,Lukas Vachathodology to formally derive register-transfer structures from descriptions at the algorithmic level via program transformations. Some experimental results at the end of the paper show how the run-time complexity of the synthesis process in our approach could be.作者: nerve-sparing 時間: 2025-3-27 12:24
Jozef Baruník,Ev?en Ko?enda,Lukas Vachaemporal operators over Boolean streams. This translation connects the specialized world of trajectory evaluation to a general-purpose logic and provides the semantic basis for connecting additional decision procedures and model checkers.作者: GULF 時間: 2025-3-27 17:11 作者: transdermal 時間: 2025-3-27 18:55 作者: 仇恨 時間: 2025-3-27 23:39
Wake-up Receiver System Level Design,ts inheritance. The current environment comprises a compiler, simulators, and code generators for the Pamette Xilinx-based board. Both languages are not only formal but based on real mathematics. We discuss why this is essential for good language design.作者: stress-response 時間: 2025-3-28 03:00 作者: CHOKE 時間: 2025-3-28 06:14
Well-Being, Happiness and Sustainability,el. We then describe how to formally verify that the model implements the instruction set. The contribution of this paper is a specification and verification method that facilitates the decomposition of microarchitectural correctness proofs using instruction-set extensions.作者: progestogen 時間: 2025-3-28 12:31 作者: oncologist 時間: 2025-3-28 17:27 作者: Pastry 時間: 2025-3-28 20:55 作者: 鴕鳥 時間: 2025-3-29 02:30 作者: 漂亮 時間: 2025-3-29 05:43 作者: 拋棄的貨物 時間: 2025-3-29 07:39
Formal Verification of Explicitly Parallel Microprocessorsel. We then describe how to formally verify that the model implements the instruction set. The contribution of this paper is a specification and verification method that facilitates the decomposition of microarchitectural correctness proofs using instruction-set extensions.作者: THROB 時間: 2025-3-29 12:44
Efficient Decompositional Model Checking for Regular Timing Diagramsar in the system size and a small polynomial in the representation of the diagram. The algorithm can be easily used with symbolic (BDDbased) model checkers. We illustrate the workings of our algorithm with the verification of a simple master-slave system.作者: 寡頭政治 時間: 2025-3-29 16:01 作者: 思想 時間: 2025-3-29 21:18 作者: CLAP 時間: 2025-3-30 02:34 作者: LIEN 時間: 2025-3-30 06:39 作者: 浪費時間 時間: 2025-3-30 11:54
Formal Synthesis at the Algorithmic Levelthodology to formally derive register-transfer structures from descriptions at the algorithmic level via program transformations. Some experimental results at the end of the paper show how the run-time complexity of the synthesis process in our approach could be.作者: abstemious 時間: 2025-3-30 13:03 作者: AXIS 時間: 2025-3-30 18:41
Verification of Infinite State Systems by Compositional Model Checkingby model checking of systems with unbounded resources and uninterpreted functions. The method is illustrated by application to an implementation of Tomasulo’s algorithm, for arbitrary or infinite word size, register file size, number of reservation stations and number of execution units.作者: Crohns-disease 時間: 2025-3-30 23:46 作者: enlist 時間: 2025-3-31 01:27
Spike Diseases Caused by Viruses,marck’s method.We show that these railway systems share important characteristics which distinguish them from most hardware designs,and that these differences raise some doubts about the applicability of St?lmarck’s method to hardware verification.作者: Resign 時間: 2025-3-31 08:09 作者: 絆住 時間: 2025-3-31 12:01
Using Symbolic Model Checking to Verify the Railway Stations of Hoorn-Kersenboogerd and Heerhugowaarmarck’s method.We show that these railway systems share important characteristics which distinguish them from most hardware designs,and that these differences raise some doubts about the applicability of St?lmarck’s method to hardware verification.作者: Infantry 時間: 2025-3-31 14:24 作者: 種族被根除 時間: 2025-3-31 19:46 作者: 演講 時間: 2025-4-1 01:45 作者: Prognosis 時間: 2025-4-1 05:08
