標題: Titlebook: Correct Hardware Design and Verification Methods; 11th IFIP WG 10.5 Ad Tiziana Margaria,Tom Melham Conference proceedings 2001 Springer-Ver [打印本頁] 作者: 助手 時間: 2025-3-21 17:17
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書目名稱Correct Hardware Design and Verification Methods讀者反饋
書目名稱Correct Hardware Design and Verification Methods讀者反饋學科排名
作者: 禁令 時間: 2025-3-21 20:28
Electrical Resonance: Solutionsas a preprocessor for a temporal scaling technique, called . [.]. The latter is applicable in reachability analysis and is included in a recent version of the Mocha model checking tool. We demonstrate performance and benefits of our method and use an asynchronous parity computer and an opinion poll 作者: stratum-corneum 時間: 2025-3-22 04:10 作者: Immortal 時間: 2025-3-22 07:04 作者: 粗魯性質(zhì) 時間: 2025-3-22 11:25
0302-9743 MCAD), which is held on even-numbered years in the USA. The conference tookplace during 4–7 September 2001 at the Institute for System Level Integration in Livingston, Scotland. It was co-hoste978-3-540-42541-0978-3-540-44798-6Series ISSN 0302-9743 Series E-ISSN 1611-3349 作者: Orchiectomy 時間: 2025-3-22 15:44 作者: Orchiectomy 時間: 2025-3-22 17:39
Heuristics for Hierarchical Partitioning with Application to Model Checkingas a preprocessor for a temporal scaling technique, called . [.]. The latter is applicable in reachability analysis and is included in a recent version of the Mocha model checking tool. We demonstrate performance and benefits of our method and use an asynchronous parity computer and an opinion poll 作者: tariff 時間: 2025-3-22 23:17
Coverability Analysis Using Symbolic Model Checkingty highlights a distinction between (1) whether a model has been covered by some test suite and (2) whether the model can ever be covered by any test suite. Coverability Analysis can be performed as soon as the hardware or software are written, before the test harness has been written.作者: FORGO 時間: 2025-3-23 01:29
View from the Fringe of the Fringerch in this area. Although it may seem relatively academic to some, it is vital that this the so-called “theorem proving approach” continue to be as vigorously explored as approaches favoring highly automated reasoning. ., a term for design formalisms based on transformations and equivalence, repres作者: Nostalgia 時間: 2025-3-23 07:15 作者: 方舟 時間: 2025-3-23 10:41
Applications of Hierarchical Verification in Model Checkingms to successfully verify a wide spectrum of large and complex circuits. This paper describes a variety of the decomposition techniques that we have used as part of a large industrial formal verification effort on the Intel Pentium? 4 (Willamette) processor.作者: dialect 時間: 2025-3-23 16:42 作者: 微不足道 時間: 2025-3-23 20:46 作者: Infect 時間: 2025-3-23 23:58
Efficient Reachability Analysis and Refinement Checking of Timed Automata Using BDDs timed automata [.]. Matrix-based algorithms for the reachability analysis of timed automata are implemented in tools like Kronos, Uppaal, HyTech and Rabbit. A new BDD-based version of Rabbit, which supports also refinement checking, is now available.作者: BRUNT 時間: 2025-3-24 05:32
Deriving Real-Time Programs from Duration Calculus SpecificationsThe main idea of our approach is to model discretization at state level by introducing the discrete states approximating the continuous ones, and then derive a specification of the control program over discrete states. Then the control program is derived from its specification using an extension of 作者: 懦夫 時間: 2025-3-24 08:10 作者: 轎車 時間: 2025-3-24 13:00
Formally-Based Design Evaluation Logic in Lotos - the ISO Language Of Temporal Ordering Specification). Relations for (strong) conformance are defined to verify a design specification against a high-level specification. Tools have been developed for automated testing and verification of conformance between an implementation and it作者: Detain 時間: 2025-3-24 17:01 作者: 帶來的感覺 時間: 2025-3-24 19:54
Register Transformations with Multiple Clock Domainsance and power requirements. In this paper, we identify a special case of multiple clocking that encompasses typical design styles, and we present a theory enabling a wide range of register transformations relating to the multiple clock domains. For example, we can perform pipelining, phase abstract作者: 有毛就脫毛 時間: 2025-3-25 00:24
Temporal Properties of Self-Timed Ringst self-timed networks, a ring, and note that for timing applications, self-timed rings should maintain uniform spacing of events. In practice, all previous designs of which we are aware cluster events into bursts. In this paper, we describe a dynamical systems approach to verify the temporal propert作者: Confirm 時間: 2025-3-25 06:48 作者: flavonoids 時間: 2025-3-25 10:17 作者: 碌碌之人 時間: 2025-3-25 15:09 作者: critique 時間: 2025-3-25 17:01
Proof Engineering in the Large: Formal Verification of Pentium?4 Floating-Point Divider all micro-operations executing on the floating-point division and square root unit of the Intel IA-32 Pentium?4 microprocessor. The verification methodology is based on combining human-guided mechanised theorem-proving with low-level steps verified by fully automated model-checking. A key observati作者: plasma-cells 時間: 2025-3-25 20:16 作者: Lumbar-Spine 時間: 2025-3-26 00:15
Conference proceedings 2001ods. CHARME 2001 is the 11th in a series of working conferences devoted to the development and use of leading-edge formal techniques and tools for the design and veri?cation of hardware and hardware-like systems. Previous events in the ‘CHARME’ series were held in Bad Herrenalb (1999), Montreal (199作者: BALK 時間: 2025-3-26 07:08
Register Transformations with Multiple Clock Domainsheory enabling a wide range of register transformations relating to the multiple clock domains. For example, we can perform pipelining, phase abstraction, and retiming across clock domain boundaries. We believe our theory will be useful to extend current work on formal hardware design, synthesis, and verification to multiple-clock-domain systems.作者: Pandemic 時間: 2025-3-26 10:45 作者: faultfinder 時間: 2025-3-26 15:14
Mark Hepworth,Siobhan Duvigneauon in the work is the need to explicitly address the issues of proof design and proof engineering, i.e. the process of creating proofs and the craft of structuring and formulating them, as concerns on their own right.作者: 消瘦 時間: 2025-3-26 19:22
Writing and Comparing Algorithms efficient implementation than a non-verified version. The approach is useful for guiding compiler implementations for Pebble and related languages such as VHDL; it may also form the basis for automating the generation of provably-correct tools for hardware development.作者: organism 時間: 2025-3-26 22:17 作者: 愛管閑事 時間: 2025-3-27 04:10
Proof Engineering in the Large: Formal Verification of Pentium?4 Floating-Point Divideron in the work is the need to explicitly address the issues of proof design and proof engineering, i.e. the process of creating proofs and the craft of structuring and formulating them, as concerns on their own right.作者: JIBE 時間: 2025-3-27 07:18
Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques efficient implementation than a non-verified version. The approach is useful for guiding compiler implementations for Pebble and related languages such as VHDL; it may also form the basis for automating the generation of provably-correct tools for hardware development.作者: 聚集 時間: 2025-3-27 10:05
Electrical Resonance: Solutionsics and internal determinism. Statements driven by different clocks communicate through two special devices called the sampler and the reclocker. Multiclock Esterel should be understood as a preliminary language proposal meant to study multiclocking. It has not yet been validated by large experiments.作者: 發(fā)現(xiàn) 時間: 2025-3-27 15:03
Multiclock Esterelics and internal determinism. Statements driven by different clocks communicate through two special devices called the sampler and the reclocker. Multiclock Esterel should be understood as a preliminary language proposal meant to study multiclocking. It has not yet been validated by large experiments.作者: Throttle 時間: 2025-3-27 21:01
Tuyet L. Cosslett,Patrick D. Cosslettng and superscalar techniques to be explored for a simple processor in the MIPS style. We also explore how ideas from partial evaluation (static and run-time data) can be used to unify the disparate approaches in Hydra/Lava/Hawk and SAFL and to allow processor specialisation.作者: dissent 時間: 2025-3-28 00:20 作者: Chemotherapy 時間: 2025-3-28 05:00 作者: 遠地點 時間: 2025-3-28 10:13 作者: Debate 時間: 2025-3-28 12:17
Reproducing Synchronization Bugs with Model Checkingto introduce non-determinism when checking a VLSI design, and because of its ability to produce counter examples for specifications that fail, we find that model checking is the ideal tool for reproducing synchronization bugs.作者: 傷心 時間: 2025-3-28 17:36
Temporal Properties of Self-Timed Ringstechniques, while providing a higher level of abstraction than non-linear differential equation models such as SPICE. Evenly spaced and clustered event behaviours are distinguished by simple geometric features of our model.作者: Binge-Drinking 時間: 2025-3-28 20:06
0302-9743 orrect Hardware Design and Veri?cation Methods. CHARME 2001 is the 11th in a series of working conferences devoted to the development and use of leading-edge formal techniques and tools for the design and veri?cation of hardware and hardware-like systems. Previous events in the ‘CHARME’ series were 作者: MUTE 時間: 2025-3-29 00:39 作者: 不朽中國 時間: 2025-3-29 06:34 作者: IOTA 時間: 2025-3-29 07:43
Lecture Notes in Computer Sciencehttp://image.papertrans.cn/c/image/238738.jpg作者: DEFT 時間: 2025-3-29 11:48
https://doi.org/10.1007/3-540-44798-9Clocking; Hardware; algorithm; algorithms; design; model; model checking; proving; theorem proving; verificat作者: 煤渣 時間: 2025-3-29 19:21
978-3-540-42541-0Springer-Verlag Berlin Heidelberg 2001作者: 連鎖,連串 時間: 2025-3-29 20:06
Correct Hardware Design and Verification Methods978-3-540-44798-6Series ISSN 0302-9743 Series E-ISSN 1611-3349 作者: Buttress 時間: 2025-3-30 01:49 作者: 旁觀者 時間: 2025-3-30 06:12 作者: 矛盾心理 時間: 2025-3-30 10:34
Sinusoidal Oscillators: ProblemsThe main idea of our approach is to model discretization at state level by introducing the discrete states approximating the continuous ones, and then derive a specification of the control program over discrete states. Then the control program is derived from its specification using an extension of Hoare triples to real-time.作者: HARP 時間: 2025-3-30 16:02 作者: ensemble 時間: 2025-3-30 17:16
I-LEARN: Information Literacy for Learners-preserving RTL transformation called ., to collectively perform the same task as that of a scheduler. Violation of the transformation precondition signals an error and the sequence of RTS transformations applied so far forms a trace which can be used for debugging purposes.作者: 圖畫文字 時間: 2025-3-30 21:41 作者: 增減字母法 時間: 2025-3-31 04:15
Applications of Hierarchical Verification in Model Checkingms to successfully verify a wide spectrum of large and complex circuits. This paper describes a variety of the decomposition techniques that we have used as part of a large industrial formal verification effort on the Intel Pentium? 4 (Willamette) processor.作者: evince 時間: 2025-3-31 05:22 作者: 不斷的變動 時間: 2025-3-31 11:10
Deriving Real-Time Programs from Duration Calculus SpecificationsThe main idea of our approach is to model discretization at state level by introducing the discrete states approximating the continuous ones, and then derive a specification of the control program over discrete states. Then the control program is derived from its specification using an extension of Hoare triples to real-time.作者: Humble 時間: 2025-3-31 14:08
Formally-Based Design Evaluation Logic in Lotos - the ISO Language Of Temporal Ordering Specification). Relations for (strong) conformance are defined to verify a design specification against a high-level specification. Tools have been developed for automated testing and verification of conformance between an implementation and its specification.作者: 魅力 時間: 2025-3-31 18:48
Verification of Basic Block Schedules Using RTL Transformations-preserving RTL transformation called ., to collectively perform the same task as that of a scheduler. Violation of the transformation precondition signals an error and the sequence of RTS transformations applied so far forms a trace which can be used for debugging purposes.作者: Diaphragm 時間: 2025-3-31 23:34
Parameterized Verification of the FLASH Cache Coherence Protocol by Compositional Model Checkingf assistant, a proof system based on symbolic model checking. The proof process is described step by step. The protocol model is derived from an earlier proof of the FLASH protocol, using the PVS system, allowing a direct comparison between the two methods.作者: GULF 時間: 2025-4-1 03:50 作者: 小官 時間: 2025-4-1 06:20
Distributed Control System Operations,The action systems formalism has recently been applied to the area of asynchronous and synchronous VLSI design. In this paper, we study formal aspects of synchronous pipelining. We show how the frame-work of synchronous action systems can be used to derive a pipelined structure from a non-pipelined specification in a correctness-preserving manner.作者: 阻擋 時間: 2025-4-1 10:55
Specifying Hardware Timing with ET-L,It is explained how Dill (Digital Logic in L.) can specify and analyse hardware timing characteristics using ET-L. (Enhanced Timed L. — the ISO Language Of Temporal Ordering Specification). Hardware functionality and timing characteristics are rigorously specified and then validated.作者: Thyroid-Gland 時間: 2025-4-1 17:51 作者: 切掉 時間: 2025-4-1 21:10
Tuyet L. Cosslett,Patrick D. Cosslettrch in this area. Although it may seem relatively academic to some, it is vital that this the so-called “theorem proving approach” continue to be as vigorously explored as approaches favoring highly automated reasoning. ., a term for design formalisms based on transformations and equivalence, repres作者: FLOUR 時間: 2025-4-2 00:30
Tuyet L. Cosslett,Patrick D. Cosslettlanguage SAFL to describe hardware computation; . transforming SAFL programs using various meaning-preserving transformations to choose the area-time position (e.g. by resource duplication/sharing, specialisation, pipelining); and . compiling the resultant program in a . manner (keeping the gross st作者: 放牧 時間: 2025-4-2 05:42
Tuyet L. Cosslett,Patrick D. Cosslettms to successfully verify a wide spectrum of large and complex circuits. This paper describes a variety of the decomposition techniques that we have used as part of a large industrial formal verification effort on the Intel Pentium? 4 (Willamette) processor.作者: 圖畫文字 時間: 2025-4-2 10:59
Electrical Resonance: Solutionsed BMC is conducted in a gradual manner, by solving a series of SAT instances corresponding to formulations of the problem with increasing .. We show how the gradual nature can be exploited for shortening the overall verification time. The concept is to reuse constraints on the search space which ar作者: anthesis 時間: 2025-4-2 12:06
