標題: Titlebook: Correct Hardware Design and Verification Methods; IFIP WG 10.2 Advance George J. Milne,Laurence Pierre Conference proceedings 1993 Springer [打印本頁] 作者: 故障 時間: 2025-3-21 17:41
書目名稱Correct Hardware Design and Verification Methods影響因子(影響力)
書目名稱Correct Hardware Design and Verification Methods影響因子(影響力)學(xué)科排名
書目名稱Correct Hardware Design and Verification Methods網(wǎng)絡(luò)公開度
書目名稱Correct Hardware Design and Verification Methods網(wǎng)絡(luò)公開度學(xué)科排名
書目名稱Correct Hardware Design and Verification Methods被引頻次
書目名稱Correct Hardware Design and Verification Methods被引頻次學(xué)科排名
書目名稱Correct Hardware Design and Verification Methods年度引用
書目名稱Correct Hardware Design and Verification Methods年度引用學(xué)科排名
書目名稱Correct Hardware Design and Verification Methods讀者反饋
書目名稱Correct Hardware Design and Verification Methods讀者反饋學(xué)科排名
作者: 樸素 時間: 2025-3-21 22:29
Logic verification of incomplete functions and design error location,o be incorrect, a conditional stuck-at fault model is proposed to represent the circuit with design errors. The incorrect logic values at the design error sites can be considered as conditional stuck-at faults. A design error locating method, based on fault simulation and released pattern generation, is described.作者: 河流 時間: 2025-3-22 03:11
A theory of generic interpreters, The generic interpreter theory provides a methodology for deriving important definitions and lemmas that were previously obtained in a largely ad hoc fashion. Many of the complex data and temporal abstractions are done in the abstract theory and need not be redone when the theory is used.作者: 預(yù)感 時間: 2025-3-22 05:28
Towards a provably correct hardware implementation of occam,d subset of occam. Algebraic laws are used to facilitate the transformation from a program into a normal form. The compiling specification is presented as a set of theorems that must be proved correct with respect to these laws. A rapid prototype compiler in the form of a logic program may be implemented from these theorems.作者: cogitate 時間: 2025-3-22 11:43 作者: forthy 時間: 2025-3-22 16:47 作者: forthy 時間: 2025-3-22 18:05
Verification and diagnosis of digital systems by ternary reasoning,ternary simulation. The verification vectors are derived from AND/OR trees. We also show how design error diagnosis can be performed by utilizing the difference vector set. Algorithms for the diagnosis of single inverter errors, and wrong gate type, are presented, together with illustrative examples.作者: Amenable 時間: 2025-3-23 01:09
A methodology for system-level design for verifiability,scription is obtained and used for validation purposes and for building the corresponding automaton. An efficient BDD-based tool for Process Algebra manipulation supports formal equivalence proofs. Experimental results show that the approach is feasible also for real-size industrial cases.作者: Postulate 時間: 2025-3-23 04:40
Calculational derivation of a counter with bounded response time,erves as the functional specification..The design is generic in that it describes counters with all possible periods. The response time as well as the power dissipation of all these counters are bounded by values that do not depend on the period.作者: 撕裂皮肉 時間: 2025-3-23 07:58 作者: Visual-Acuity 時間: 2025-3-23 13:05 作者: Cardioversion 時間: 2025-3-23 14:14 作者: Relinquish 時間: 2025-3-23 20:52 作者: 船員 時間: 2025-3-23 23:41
Tuyet L. Cosslett,Patrick D. Cosslettd subset of occam. Algebraic laws are used to facilitate the transformation from a program into a normal form. The compiling specification is presented as a set of theorems that must be proved correct with respect to these laws. A rapid prototype compiler in the form of a logic program may be implemented from these theorems.作者: Biguanides 時間: 2025-3-24 04:14 作者: 斑駁 時間: 2025-3-24 10:17 作者: Ruptured-Disk 時間: 2025-3-24 11:55 作者: 花爭吵 時間: 2025-3-24 14:59
Heming Wen,Prabhat Kumar Tiwary,Tho Le-Ngocossible behaviors for the system. The ability to represent and reason about time ranges for events is a distinguishing characteristic of our technique and gives our analysis method both its power and complexity.作者: Arthropathy 時間: 2025-3-24 19:07
Integrated Urban Water Resources Management,ternary simulation. The verification vectors are derived from AND/OR trees. We also show how design error diagnosis can be performed by utilizing the difference vector set. Algorithms for the diagnosis of single inverter errors, and wrong gate type, are presented, together with illustrative examples.作者: 舊石器 時間: 2025-3-25 02:13 作者: 反叛者 時間: 2025-3-25 05:59
Tuyet L. Cosslett,Patrick D. Cossletterves as the functional specification..The design is generic in that it describes counters with all possible periods. The response time as well as the power dissipation of all these counters are bounded by values that do not depend on the period.作者: chisel 時間: 2025-3-25 07:37
Tuyet L. Cosslett,Patrick D. Cosslettoses the verification goal by a set of hardware-specific proof tactics and provides strategies for synthesizing pre-verified regular components. In case of erroneous implementations, MEPHISTO aids the designer in debugging the circuit by generating a counter model, i.e. input stimuli where specification and implementation behave differently.作者: interrogate 時間: 2025-3-25 11:44
Water and the Future of Humanityo formal synthesis, (a process whereby one starts with a behavioural specification and, using an interactive goal-directed approach, ends up with a circuit and a formal proof that it satisfies the given behavioural specification).作者: HAVOC 時間: 2025-3-25 18:31
or. A theoretical result allows us to considerably simplify both the process of building the transition relation and of traversing the state space. Experimental results show that performances similar to those of the transition function are obtained.作者: 檔案 時間: 2025-3-25 22:31
per describes the derivation of the DDD-FM9001 and compares the derived architecture and hardware realization with that of the FM9001 in an effort to better understand the interplay between derivation and verification.作者: 障礙 時間: 2025-3-26 01:09 作者: 賄賂 時間: 2025-3-26 06:01 作者: Dignant 時間: 2025-3-26 08:37 作者: DEFER 時間: 2025-3-26 15:13
Conference proceedings 1993ce, in May 1993,and organized by the ESPRIT Working Group 6018 CHARME-2andthe Universit de Provence, Marseille, in cooperation withIFIPWorking Group 10.2.Formal verification is emerging as a plausiblealternativeto exhaustive simulation for establishing correct digitalhardware designs. The validation作者: 案發(fā)地點 時間: 2025-3-26 18:25 作者: Immobilize 時間: 2025-3-26 22:36
A Petri Net approach for the analysis of VHDL descriptions,hniques of Petri nets. The bad behaviours that we consider concern the execution control flow of a VHDL description. This methodology works in three steps. First, a formal description in Petri Net terms of the execution control flow of a VHDL description is realized. We present the basic rules to pe作者: enlist 時間: 2025-3-27 02:49 作者: 說不出 時間: 2025-3-27 06:04 作者: Lipoprotein 時間: 2025-3-27 11:30
Verification and diagnosis of digital systems by ternary reasoning,rmal verification by ternary simulation is feasible. In this paper, we demonstrate that complete verification of Finite State Machines is possible by ternary simulation. The verification vectors are derived from AND/OR trees. We also show how design error diagnosis can be performed by utilizing the 作者: Vertebra 時間: 2025-3-27 14:12
Logic verification of incomplete functions and design error location,l circuit. For an incompletely specified function, a method to compute the corresponding 3-terminal BDD that represents the ON-set, OFF-set and DC-set, is described. Two incomplete functions are equivalent if, and only if, their 3-terminal BDDs are isomorphic. If the gate-level circuit is verified t作者: 小丑 時間: 2025-3-27 18:35
A methodology for system-level design for verifiability,is paper presents a system-level design methodology that supports verification. Starting from a description in a proper subset of VHDL, a Petri Net description is obtained and used for validation purposes and for building the corresponding automaton. An efficient BDD-based tool for Process Algebra m作者: 放牧 時間: 2025-3-28 01:52 作者: 革新 時間: 2025-3-28 05:25
Combining symbolic evaluation and object oriented approach for verifying processor-like architecture RT-level. We develop a new method which combines the extensibility and flexibility of object oriented programming paradigm and the efficiency of a specialized computer algebra system. An object oriented programming is naturally well-adapted to express the behaviour associated to each category of c作者: 褻瀆 時間: 2025-3-28 09:03 作者: 煞費苦心 時間: 2025-3-28 11:20
Towards verifying large(r) systems: A strategy and an experiment,not yet feasible on a routine basis. The goal of the work discussed here is to enable the verification of large(r) real systems than currently feasible with any one of the available techniques, and to dovetail the verification methodology with the an underlying design methodology. The specific desig作者: 耕種 時間: 2025-3-28 16:53 作者: 有發(fā)明天才 時間: 2025-3-28 21:40 作者: 混亂生活 時間: 2025-3-29 01:49
Correct compilation of specifications to deterministic asynchronous circuits,component, mutual exclusion violations, fairness, handshaking variables, distinguished ports, equational rewriting, separate compilation and observable determinism were introduced..Two recent papers address the same general problem of proving correctness of asynchronous circuit compilation [WBB92, v作者: landfill 時間: 2025-3-29 06:12 作者: CHOP 時間: 2025-3-29 08:41 作者: 敲竹杠 時間: 2025-3-29 14:20
Towards a provably correct hardware implementation of occam, be loaded into a . (FPGA). A simple state-machine model is adopted for specifying the behaviour of a synchronous circuit where the observable includes the state of the control path and the data path of the circuit. We identify the behaviour of a circuit with a program consisting of a very restricte作者: 彎彎曲曲 時間: 2025-3-29 19:24
Rewriting with constraints in T-ruby,s method is based on syntactic rewriting of Ruby terms, combined with the introduction of constraints into the specification. The rewriting process is described in a meta-language based on the use of tactics and tacticals, which makes it possible to develop complex specialised strategies for the ref作者: LATER 時間: 2025-3-29 21:19
Embedding hardware verification within a commercial design framework,s goal has been achieved by integrating MEPHISTO, a tool for semi-automated hardware verification, into a commercial design framework. MEPHISTO decomposes the verification goal by a set of hardware-specific proof tactics and provides strategies for synthesizing pre-verified regular components. In ca作者: 善于騙人 時間: 2025-3-30 03:08 作者: 勉強 時間: 2025-3-30 06:59
The Nordic Model and Social Inequalities,cation and design. We apply this iterated map method to the top level ., and to an abstract implementation, the .. We formalise what it means for the implementation to correctly implement the specification. We illustrate the iterated map method with a case study.作者: 軍械庫 時間: 2025-3-30 12:07 作者: 飛鏢 時間: 2025-3-30 13:33
s method is based on syntactic rewriting of Ruby terms, combined with the introduction of constraints into the specification. The rewriting process is described in a meta-language based on the use of tactics and tacticals, which makes it possible to develop complex specialised strategies for the refinement of specifications.作者: Semblance 時間: 2025-3-30 19:27 作者: macular-edema 時間: 2025-3-30 22:05 作者: savage 時間: 2025-3-31 03:26 作者: 使混合 時間: 2025-3-31 08:21 作者: glomeruli 時間: 2025-3-31 10:46
Heming Wen,Prabhat Kumar Tiwary,Tho Le-Ngocis paper, we describe our analysis technique which accepts a behavioral specification of the timing of a digital system and generates the set of all possible behaviors for the system. The ability to represent and reason about time ranges for events is a distinguishing characteristic of our technique作者: COKE 時間: 2025-3-31 16:50 作者: 犬儒主義者 時間: 2025-3-31 19:09
Integrated Urban Water Resources Management,rmal verification by ternary simulation is feasible. In this paper, we demonstrate that complete verification of Finite State Machines is possible by ternary simulation. The verification vectors are derived from AND/OR trees. We also show how design error diagnosis can be performed by utilizing the 作者: PRO 時間: 2025-4-1 00:59 作者: squander 時間: 2025-4-1 05:39
Water for a Healthy Environment,is paper presents a system-level design methodology that supports verification. Starting from a description in a proper subset of VHDL, a Petri Net description is obtained and used for validation purposes and for building the corresponding automaton. An efficient BDD-based tool for Process Algebra m作者: 枯萎將要 時間: 2025-4-1 06:06
The Nordic Model and Social Inequalities,cation and design. We apply this iterated map method to the top level ., and to an abstract implementation, the .. We formalise what it means for the implementation to correctly implement the specification. We illustrate the iterated map method with a case study.作者: burnish 時間: 2025-4-1 10:53
Background: Banking and Causality,e RT-level. We develop a new method which combines the extensibility and flexibility of object oriented programming paradigm and the efficiency of a specialized computer algebra system. An object oriented programming is naturally well-adapted to express the behaviour associated to each category of c作者: Interferons 時間: 2025-4-1 15:49
Background: Banking and Causality,system specification and verification. The generic interpreter theory contains an abstract representation which serves as an interface to the theory and as a guide to specification. A set of theory obligations ensure that the theory is being used correctly and provide a guide to system verification.作者: scotoma 時間: 2025-4-1 20:23 作者: Tinea-Capitis 時間: 2025-4-2 00:54
ansition functions and transition relations are two alternative approaches. In terms of efficiency, transition functions have proven to be superior, although the transition relation is much more expressive. This paper brings the transition relation back to a new life, profiting from recent advanceme作者: 考古學(xué) 時間: 2025-4-2 06:46
Background: Banking and Causality,implementation. The Circal system is able to check equivalence between terms of the Circal process algebra. The system can be used to verify the results of some of Martin‘s refinements and the gate implementations. It can also be used to analyse the operator network for the necessity of isochronic f
