標題: Titlebook: Computer Engineering and Technology; 20th CCF Conference, Weixia Xu,Liquan Xiao,Zhenzhen Zhu Conference proceedings 2016 Springer Nature Si [打印本頁] 作者: osteomalacia 時間: 2025-3-21 18:21
書目名稱Computer Engineering and Technology影響因子(影響力)
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書目名稱Computer Engineering and Technology被引頻次學(xué)科排名
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作者: 無價值 時間: 2025-3-21 21:53
W. Erwin Diewert,Denis A. Lawrence-bit coarse directory, 22% overhead of share list can be avoided at the expense of 0.16% average performance loss on average; compared to 8-bit coarse directory, 48% invalid messages are saved and the performance is improved by 2.31%.作者: 初次登臺 時間: 2025-3-22 03:00
https://doi.org/10.1057/9780230375260he efficiency of our implementation of NKICA on the MIC architecture, and show that it achieves a consistent speedup rate of around 10 on average, and of 12.3 at best, comparing with that performed on single CPU.作者: 極小量 時間: 2025-3-22 05:19 作者: SHOCK 時間: 2025-3-22 08:58
BFDir: A Space-Efficient Coherence Directory Based on Bloom Filter-bit coarse directory, 22% overhead of share list can be avoided at the expense of 0.16% average performance loss on average; compared to 8-bit coarse directory, 48% invalid messages are saved and the performance is improved by 2.31%.作者: Carcinoma 時間: 2025-3-22 14:21 作者: Carcinoma 時間: 2025-3-22 20:33
Single/Double Precision Floating-Point Division and Square Root Unit Based on SRT-8 Algorithm-precision/SIMD single-precision floating-point division and square root operation based on SRT-8 algorithm was introduced. Special instructions were designed and independent mantissa computing unit and normalization unit are implemented. Moreover, parallel adders and QDS structure was adopted to hi作者: 輪流 時間: 2025-3-23 01:07 作者: FLAGR 時間: 2025-3-23 03:11
A Methodology for Performance Verification of Microprocessorsten introduced during the design stages. In order to identify and fix the performance defects, a hierarchical performance verification methodology is proposed. Parameter sensitive performance models and coverage driven stimulus are built at the unit-level. Implementation oriented performance calibra作者: 下船 時間: 2025-3-23 05:40
A Novel L1 Cache Based on Volatile STT-RAMscalability, high density and low leakage power. Nevertheless, the current non-volatile STT-RAM cache architecture also has some drawbacks, such as long write latency and high write energy, which limit the application of STT-RAM in the top level cache design. To solve these problems, we relax the re作者: 咒語 時間: 2025-3-23 13:38 作者: enchant 時間: 2025-3-23 16:50 作者: chiropractor 時間: 2025-3-23 19:07 作者: Toxoid-Vaccines 時間: 2025-3-23 22:44 作者: Baffle 時間: 2025-3-24 03:22 作者: 殺人 時間: 2025-3-24 08:51 作者: Vertical 時間: 2025-3-24 12:48 作者: 損壞 時間: 2025-3-24 16:39
A Channel-Level RAID5 Schema Based Physical Address in SSD capacity, the reliability problem of SSD is becoming increasingly serious. In this paper, we implemented a technique based SSDs by constructing RAID-5 to enhance the reliability of SSD while maintaining its performance. First, we construct RAID-5 stripe based on SSD physical address which means no 作者: Meditative 時間: 2025-3-24 20:23 作者: 拱形大橋 時間: 2025-3-25 02:49 作者: 圓錐體 時間: 2025-3-25 04:45
An AWGR-Based High Performance Optical Interconnect Architecture for Exascale Systemsizing exascale computing is the fundamental challenge of communication networks. We propose a high performance optical interconnect architecture based on Arrayed waveguide grating router (AWGR) with WDM wavelength routing, the inherent parallelism in AWGRs and multi-hop switching provide high scalab作者: 東西 時間: 2025-3-25 07:44
Accelerating Nystr?m Kernel Independent Component Analysis with Many Integrated Core Architecturel in many practical tasks such as speech separation due to its robustness on varying source distributions. Recently, Nystr?m-KICA (NKICA) incorporates a low-rank approximation and low-complexity sampling method to reduce the computational complexity of KICA. In this paper, we show that the computati作者: Mercurial 時間: 2025-3-25 14:59
Conference proceedings 2016 August 2016.?.The 21 full papers presented were carefully reviewed and selected from 120 submissions. They are organized in topical sections on processor architecture; application specific processors; computer application and software optimization; technology on the horizon..作者: FORGO 時間: 2025-3-25 17:59
1865-0929 are organized in topical sections on processor architecture; application specific processors; computer application and software optimization; technology on the horizon..978-981-10-3158-8978-981-10-3159-5Series ISSN 1865-0929 Series E-ISSN 1865-0937 作者: 爆米花 時間: 2025-3-25 22:19 作者: 半導(dǎo)體 時間: 2025-3-26 04:11 作者: Vertical 時間: 2025-3-26 08:21
Opinions on Tax Evasion in Armeniatention time of STT-RAM to explore its different write performance, and propose a novel STT-RAM L1 cache architecture implemented with volatile STT-RAM as well as its related refresh scheme. The performance of proposed design is the same as SRAM L1 cache while its overall power consumption is only 63.8% of the latter one.作者: 有角 時間: 2025-3-26 12:07
Robert W. McGee,Marcelo J. Rossitional single-threshold algorithm, experimental results show that dual-threshold adaptive DVFS can save more power with no obviously performance reduction. The performance of most benchmarks is beyond 90% of the original performance, while the power optimization can be up to 35%.作者: arousal 時間: 2025-3-26 16:01 作者: 周年紀念日 時間: 2025-3-26 18:23 作者: Hallowed 時間: 2025-3-26 22:57
,Into the Labyrinth (1955–1976),rt DCT, the proposed architecture dissipates 8.2% less power and improves PSNR by 3.21?dB while maintaining nearly the same area and speed. The proposed architecture uses 37.6% less hardware resources, saves 31.6% in power dissipation, provides a 2.15 times speed-up and improves PSNR slightly when compared with the newest DCT/IDCT architecture.作者: 使出神 時間: 2025-3-27 02:05
Taxation and Employment in New Zealandt of hardware resource usage. Based on the proposed architecture, we implemented a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder on a Xilinx Kintex7 (XC7K325T-2) board. The FPGA implementation results show that the decoder can achieve a total decoding throughput of 1.6?Gbps at the clock frequency of 105Mth at 10 iterations.作者: 子女 時間: 2025-3-27 06:22
https://doi.org/10.1057/9780230375260 on Arrayed waveguide grating router (AWGR) with WDM wavelength routing, the inherent parallelism in AWGRs and multi-hop switching provide high scalability of the network. Theoretical analysis and simulation show its better performance compared with fat-tree architecture.作者: 脆弱么 時間: 2025-3-27 11:03 作者: 成績上升 時間: 2025-3-27 14:36 作者: 思想 時間: 2025-3-27 19:28
An AWGR-Based High Performance Optical Interconnect Architecture for Exascale Systems on Arrayed waveguide grating router (AWGR) with WDM wavelength routing, the inherent parallelism in AWGRs and multi-hop switching provide high scalability of the network. Theoretical analysis and simulation show its better performance compared with fat-tree architecture.作者: Deadpan 時間: 2025-3-28 01:32
https://doi.org/10.1007/978-3-031-58124-3 We use LEVCS to vectorize five benchmark kernels: Fast Fourier Transform (FFT), Finite Impulse Responsefilter (FIR) and Infinite Impulse Response filter (IIR), Dot product implementation (Dotprod), Sum of vectors (vecsum). Experiment results show that LEVCS is functional correct and can achieve 2.883–8.074 speedups comparing to TI-DSPs.作者: hypotension 時間: 2025-3-28 02:27 作者: Harridan 時間: 2025-3-28 08:54 作者: 不給啤 時間: 2025-3-28 11:52 作者: 拖網(wǎng) 時間: 2025-3-28 15:26 作者: 包租車船 時間: 2025-3-28 20:18
Language-Extension-Based Vectorizing Compiling Scheme on SDR-DSP We use LEVCS to vectorize five benchmark kernels: Fast Fourier Transform (FFT), Finite Impulse Responsefilter (FIR) and Infinite Impulse Response filter (IIR), Dot product implementation (Dotprod), Sum of vectors (vecsum). Experiment results show that LEVCS is functional correct and can achieve 2.883–8.074 speedups comparing to TI-DSPs.作者: fulcrum 時間: 2025-3-29 00:26
A Dynamic Multi-precision Fixed-Point Data Quantization Strategy for Convolutional Neural Network2% to 5.9% at most, compared with previous static quantization strategy, when 8/4-bit quantization is used. When 16-bit quantization is used, only 0.03% accuracy loss is introduced by our quantization strategy with half memory footprint and bandwidth requirement comparing with 32-bit floating-point implementation.作者: Bucket 時間: 2025-3-29 05:01 作者: Fulminate 時間: 2025-3-29 07:22 作者: 光明正大 時間: 2025-3-29 12:33
Monaural Speech Separation on Many Integrated Core Architecturehitecture to meet the requirement of real-time speech separation. This approach conducts parallelism based on the OpenMP technology, and performs the computing intensitive matrix manipulations on a MIC coprocessor. The experimental results confirm the efficiency of our implementation of monaural speech separation on MIC architecture.作者: 地名表 時間: 2025-3-29 18:49
Single/Double Precision Floating-Point Division and Square Root Unit Based on SRT-8 Algorithmde the latency of look-up table, generating fast addend was used to decrease critical path, and “On-the-fly” conversion was employed for saving area-cost. Experimental results show that our proposed design can achieve low latency and low hardware overhead.作者: 大氣層 時間: 2025-3-29 23:45
A Methodology for Performance Verification of Microprocessorstion and RTL simulation based benchmarks are made at the core-level. Prototyping and counter-based performance analysis systems are built in the system level. An example is given to demonstrate the application and effectiveness of the proposed methodology.作者: 樸素 時間: 2025-3-30 02:50 作者: 草率男 時間: 2025-3-30 05:18
A New DVFS Algorithm Design for Multi-core Processor Chiptional single-threshold algorithm, experimental results show that dual-threshold adaptive DVFS can save more power with no obviously performance reduction. The performance of most benchmarks is beyond 90% of the original performance, while the power optimization can be up to 35%.作者: 刺耳的聲音 時間: 2025-3-30 09:03 作者: dandruff 時間: 2025-3-30 12:25
Weixia Xu,Liquan Xiao,Zhenzhen ZhuIncludes supplementary material: 作者: 修飾語 時間: 2025-3-30 19:00 作者: Lipoma 時間: 2025-3-30 22:14
https://doi.org/10.1007/978-3-031-58124-3-precision/SIMD single-precision floating-point division and square root operation based on SRT-8 algorithm was introduced. Special instructions were designed and independent mantissa computing unit and normalization unit are implemented. Moreover, parallel adders and QDS structure was adopted to hi作者: Ambulatory 時間: 2025-3-31 03:30
https://doi.org/10.1007/978-3-031-58124-3tware-Defined Radio (SDR) and is called SDR-DSP. The SDR-DSP architecture mixes the styles of VLIW (Very Long Instruction Word) and SIMD (Single Instruction Multiple Data). To explore the potential of SDR-DSP and achieve high performance, vectorization is one of the must equipped critical methods. B作者: 刻苦讀書 時間: 2025-3-31 06:44 作者: magnanimity 時間: 2025-3-31 11:06
Opinions on Tax Evasion in Armeniascalability, high density and low leakage power. Nevertheless, the current non-volatile STT-RAM cache architecture also has some drawbacks, such as long write latency and high write energy, which limit the application of STT-RAM in the top level cache design. To solve these problems, we relax the re作者: Nibble 時間: 2025-3-31 17:23
Robert W. McGee,Marcelo J. Rossiroblem making the performance improvement slow down. Therefore, how to optimize the power consumption of multi-core processor is a crisis in processor design. This paper proposes a dual-threshold adaptive DVFS algorithm to dynamically control the processor voltage and frequency. Comparing with tradi
