標(biāo)題: Titlebook: Computer Engineering and Technology; 16th National Confer Weixia Xu,Liquan Xiao,Chengyi Zhang Conference proceedings 2013 Springer-Verlag B [打印本頁] 作者: 多話 時(shí)間: 2025-3-21 17:58
書目名稱Computer Engineering and Technology影響因子(影響力)
書目名稱Computer Engineering and Technology影響因子(影響力)學(xué)科排名
書目名稱Computer Engineering and Technology網(wǎng)絡(luò)公開度
書目名稱Computer Engineering and Technology網(wǎng)絡(luò)公開度學(xué)科排名
書目名稱Computer Engineering and Technology被引頻次
書目名稱Computer Engineering and Technology被引頻次學(xué)科排名
書目名稱Computer Engineering and Technology年度引用
書目名稱Computer Engineering and Technology年度引用學(xué)科排名
書目名稱Computer Engineering and Technology讀者反饋
書目名稱Computer Engineering and Technology讀者反饋學(xué)科排名
作者: saphenous-vein 時(shí)間: 2025-3-21 21:41
Hardware Architecture for the Parallel Generation of Long-Period Random Numbers Using MT Methody pseudo-random number generators(PRNG) based on binary linear recurrences. In this paper, a hardware architecture for the generation of parallel long-period random numbers using MT19937 method was proposed. Our design is implemented on a Xilinx XC6VLX240T FPGA device and is capable of producing mul作者: Modify 時(shí)間: 2025-3-22 00:28
MGTE: A Multi-level Hybrid Verification Platform for a 16-Core Processoringly important. In this paper, a multi-level hybrid verification platform called MGTE is designed and developed for a 16-core processer PX-16. MGTE supports software simulating and hardware emulating in module level, sub-system level or full-chip level, which is capable of verifying the processor d作者: 脆弱帶來 時(shí)間: 2025-3-22 04:50 作者: poliosis 時(shí)間: 2025-3-22 11:20
A Study of Cache Design in Stream Processor processor and it aims at exploiting the parallelism and locality of the applications. In this paper, first, we inspect the memory access characteristics of FT64 with cache and without cache. Second, we propose an improved cache design method. Making use of the feature of stream data type used by FT作者: 帽子 時(shí)間: 2025-3-22 13:07
Design and Implementation of Dynamically Reconfigurable Token Coherence Protocol for Many-Core Procency (like snoopy protocol) or not depending on bus-like interconnects (like directory protocol). Recently, Token Coherence has been proposed to capture the main characteristic of traditional protocols. However, since Token Coherence relies on broadcast-based transient request and inefficient persist作者: 帽子 時(shí)間: 2025-3-22 21:00 作者: Desert 時(shí)間: 2025-3-22 21:25
ADL and High Performance Processor Designessor design, lots of institutes and companies use ADL as processor quick prototype design language and use it to generate processor simulator, test-benches and compiler utilities. This paper analyzes and compares three processor description languages. We also give the disadvantages of modern ADL wh作者: 弄污 時(shí)間: 2025-3-23 03:42 作者: Abutment 時(shí)間: 2025-3-23 06:06
A Hardware Implementation of Nussinov RNA Folding Algorithmarallelism of this kind of algorithms is one of the most relevant areas in computational biology. In this paper, we propose a parallel way to implement the Nussinov algorithm on hardware. We implement our work on Xilinx FPGA, the total clock cycles to accomplish the algorithm is about half of using 作者: 尖 時(shí)間: 2025-3-23 13:18
A Configurable Architecture for 1-D Discrete Wavelet Transformf filters with different lengths. The architecture adopts polyphase filter structure and MAC loop based filter (MLBF) to achieve high computing performance and strong generality of the system. Loop unrolling approach is used to eliminate the data hazards caused by pipelining. The hardware usage of t作者: Graduated 時(shí)間: 2025-3-23 14:46
A Comparison of Folded Architectures for the Discrete Wavelet Transform architecture to enhance hardware utilization. This work compares folded architectures for DWT based on three filter structures, the direct form filter, the linear systolic array, and the lifting structure. We generalize the design of these architectures in terms of DWT levels, filter taps and pipel作者: 恩惠 時(shí)間: 2025-3-23 19:09
A High Performance DSP System with Fault Tolerant for Space Missions high required on system performance. Conventional techniques mainly focus on the system reliability, at the expense of system performance..In this paper, a flexible, DPS-based, high-performance system is presented. The system could dynamically adapt the system’s level of redundancy according to var作者: 協(xié)迫 時(shí)間: 2025-3-24 01:27 作者: Exonerate 時(shí)間: 2025-3-24 02:32
A Word-Length Optimized Hardware Gaussian Random Number Generator Based on the Box-Muller Method word-length optimization model is proposed to find out the optimal word-lengths for signals. Experimental results show that our word-length optimized Fixed-Point generator runs as fast as 403.7 MHz on a Xilinx Virtex-6 FPGA device and is capable of generating 2 samples every clock cycle, which is 1作者: 哀求 時(shí)間: 2025-3-24 08:43
DAMQ Sharing Scheme for Two Physical Channels in High Performance Routerorts and channels, but all of which incur significant overheads in hardware costs. In this paper we present a dual-port shared buffer scheme for router. The proposed scheme is based on a dynamically allocated multi queue and four-port Register File. Two physical channels share the same input buffer 作者: Intentional 時(shí)間: 2025-3-24 14:19
Design and Implementation of Dynamic Reliable Virtual Channel for Network-on-Chip challenge for NoC(Network-on-Chip). The router is a core element of the NoC, and the virtual channel based on flip-flop which occupies most of the area is the most sensitive element to soft error of the router. Focus on this problem, a dynamic reliable virtual channel architecture is proposed in th作者: 糾纏 時(shí)間: 2025-3-24 18:44
HCCM: A Hierarchical Cross-Connected Mesh for Network on Chip structure plays a decisive role on the area and performance of system on chip, and has a profound influence on the transmission capability of system. Based on the distributed routing lookup, we proposed a new kind of inerratic interconnection network is named HCCM (Hierarchical Cross-Connected Mesh作者: 輕快走過 時(shí)間: 2025-3-24 21:26 作者: FATAL 時(shí)間: 2025-3-25 00:46
1865-0929 ional Conference on Computer Engineering and Technology, NCCET 2012, held in Shanghai, China, in August 2012. The 27 papers presented were carefully reviewed and selected from 108 submissions. They are organized in topical sections named: microprocessor and implementation; design of integration circ作者: 障礙物 時(shí)間: 2025-3-25 06:42 作者: 原始 時(shí)間: 2025-3-25 09:26 作者: trigger 時(shí)間: 2025-3-25 14:48
Tax Incentives for the Art Markett the Nussinov algorithm on hardware. We implement our work on Xilinx FPGA, the total clock cycles to accomplish the algorithm is about half of using software in serial way, and we also partly resolve the limitation of fixed length requirement of existing hardware implementation with an efficient resource usage.作者: thyroid-hormone 時(shí)間: 2025-3-25 18:23
Tax Incentives Crossing Bordersmance and strong generality of the system. Loop unrolling approach is used to eliminate the data hazards caused by pipelining. The hardware usage of the configurable architecture is fixed for any kind of wavelet functions.作者: 半身雕像 時(shí)間: 2025-3-25 22:41 作者: Innovative 時(shí)間: 2025-3-26 02:33
ADL and High Performance Processor Designenches and compiler utilities. This paper analyzes and compares three processor description languages. We also give the disadvantages of modern ADL when used in high performance processor design and give some suggestions for further ADL development.作者: 轉(zhuǎn)折點(diǎn) 時(shí)間: 2025-3-26 05:54
A Hardware Implementation of Nussinov RNA Folding Algorithmt the Nussinov algorithm on hardware. We implement our work on Xilinx FPGA, the total clock cycles to accomplish the algorithm is about half of using software in serial way, and we also partly resolve the limitation of fixed length requirement of existing hardware implementation with an efficient resource usage.作者: thalamus 時(shí)間: 2025-3-26 11:42 作者: 就職 時(shí)間: 2025-3-26 13:13 作者: Fibroid 時(shí)間: 2025-3-26 20:04
Hardware Architecture for the Parallel Generation of Long-Period Random Numbers Using MT Methodtiple samples each period. This performance let us obtain higher throughput than the non-parallelization architecture and software. The samples generated by our design are applied to a Monte Carlo simulation for estimating the value of ., and we achieve the accuracy of 99.99%.作者: 能得到 時(shí)間: 2025-3-26 21:40
MGTE: A Multi-level Hybrid Verification Platform for a 16-Core Processoruring all the design periods from details to the whole. Also, MGTE supports the hybrid verification of behavior models, RTL codes and net lists, which is capable of improving the simulation performance. It’s proved that MGTE can effectively ease the functional verification and preliminary performance evaluation of PX-16 processor.作者: Crohns-disease 時(shí)間: 2025-3-27 01:49 作者: genuine 時(shí)間: 2025-3-27 07:04 作者: 大吃大喝 時(shí)間: 2025-3-27 13:30
Georg Winckler (Professor of Economics)tiple samples each period. This performance let us obtain higher throughput than the non-parallelization architecture and software. The samples generated by our design are applied to a Monte Carlo simulation for estimating the value of ., and we achieve the accuracy of 99.99%.作者: 劇毒 時(shí)間: 2025-3-27 16:12 作者: sterilization 時(shí)間: 2025-3-27 20:40
Other Sources of Ordinary Incomersity. In this paper, we design and realize a campus information release platform based on Android framework. This campus information release platform can effectively reduce the complexity of the information release system and strengthen the real-time performance of information, which thereby promote the information construction of the campus.作者: Bridle 時(shí)間: 2025-3-28 00:20 作者: 廚師 時(shí)間: 2025-3-28 06:09
Giuseppe Bisconti,Bruno Gangemi performance has been improved by 20.7% and 25.8% when a normal cache and an improved cache are used respectively. Finally, we study on the performance influence of cache capacity and associativity. The results show that better performance can be achieved when we use a small cache and an associativity of 2 or 4.作者: 畫布 時(shí)間: 2025-3-28 09:28
Summary of Other Developed Country Laws a dynamically reconfigurable mechanism to Token Coherence. Basing on sub-net, this mechanism can significantly reduce the average execution time and communication cost in 16-core processor. Therefore, this dynamically reconfigurable mechanism makes Token Coherence applicable in many-core architecture.作者: osteocytes 時(shí)間: 2025-3-28 13:35
Summary of Other Developed Country Lawsicating subtasks on adjacent PEs according to data dependency and communication dependency. Compared with the existing algorithms, our mapping algorithm can reduce the total execution time and enhance the system throughput by 10% in simulations.作者: 表示向下 時(shí)間: 2025-3-28 14:48 作者: 我邪惡 時(shí)間: 2025-3-28 20:58 作者: Ceramic 時(shí)間: 2025-3-28 22:59 作者: GLUT 時(shí)間: 2025-3-29 05:21
https://doi.org/10.1007/978-1-4302-4738-8(triple modular redundancy) requirements in flexibility. Compared with typical TMR virtual channel design, the synthesis results show that our method can achieve several fault tolerant structures switch with near 3 times resource utilization in ideal case and only 13.8% extra area cost.作者: 萬靈丹 時(shí)間: 2025-3-29 09:53 作者: 職業(yè)拳擊手 時(shí)間: 2025-3-29 12:00
Tax Modelling for Economies in Transitioneme based on multicast XY routing algorithm is carried out. The Gem5 Simulator is used to promote the research, experimental results shows our approach have a quite less average packet latency compared with multiple unicast.作者: 固執(zhí)點(diǎn)好 時(shí)間: 2025-3-29 19:09 作者: 合乎習(xí)俗 時(shí)間: 2025-3-29 23:21 作者: 細(xì)查 時(shí)間: 2025-3-30 01:10
Design and Implementation of Dynamically Reconfigurable Token Coherence Protocol for Many-Core Proce a dynamically reconfigurable mechanism to Token Coherence. Basing on sub-net, this mechanism can significantly reduce the average execution time and communication cost in 16-core processor. Therefore, this dynamically reconfigurable mechanism makes Token Coherence applicable in many-core architecture.作者: Longitude 時(shí)間: 2025-3-30 05:35
Dynamic and Online Task Scheduling Algorithm Based on Virtual Compute Group in Many-Core Architecturicating subtasks on adjacent PEs according to data dependency and communication dependency. Compared with the existing algorithms, our mapping algorithm can reduce the total execution time and enhance the system throughput by 10% in simulations.作者: Anguish 時(shí)間: 2025-3-30 10:36
A High Performance DSP System with Fault Tolerant for Space Missionsation methods also be mentioned. In this paper, the system performances are evaluated and analyzed. With running of the correlation function benchmark in this system, it is shown that the system provides high performances under the premise of certified reliability.作者: Osteons 時(shí)間: 2025-3-30 14:16 作者: Admonish 時(shí)間: 2025-3-30 18:33
DAMQ Sharing Scheme for Two Physical Channels in High Performance Routerdetailed organization of shared buffer and management of idle buffer. Result of simulation shows that the proposed method has similar performance using only 75% of the buffer size in traditional implementation and outperforms by 5% to 10% in throughput with the same size.作者: Genteel 時(shí)間: 2025-3-30 23:22 作者: Monocle 時(shí)間: 2025-3-31 03:43
HCCM: A Hierarchical Cross-Connected Mesh for Network on Chip paper comes up with a new hierarchical routing algorithm——HXY (Hierarchical XY), the simulation results demonstrate the HCCM topology is superior to the Mesh and the Xmesh topology on the performance of system average communication delay and normalized throughput.作者: 平庸的人或物 時(shí)間: 2025-3-31 07:33
Efficient Broadcast Scheme Based on Sub-network Partition for Many-Core CMPs on Gem5 Simulatoreme based on multicast XY routing algorithm is carried out. The Gem5 Simulator is used to promote the research, experimental results shows our approach have a quite less average packet latency compared with multiple unicast.作者: Frenetic 時(shí)間: 2025-3-31 12:08
Tax Incentives for the Audio Visual Industrypression system is analyzed through experiments. The result shows that the hardware accelerator achieves the function of ROHC packet header compression protocol correctly, and significantly reduces the overhead of packet headers to effectively improve the link utilization; at the same time has good usability and flexibility.作者: 小步走路 時(shí)間: 2025-3-31 16:50 作者: expunge 時(shí)間: 2025-3-31 19:19
The Design of the ROHC Header Compression Acceleratorpression system is analyzed through experiments. The result shows that the hardware accelerator achieves the function of ROHC packet header compression protocol correctly, and significantly reduces the overhead of packet headers to effectively improve the link utilization; at the same time has good usability and flexibility.作者: 包裹 時(shí)間: 2025-3-31 22:39
A Comparison of Folded Architectures for the Discrete Wavelet Transform, filter taps and pipeline insertions have different impacts on the three architectures. Overall, the folded architecture based on lifting structure gives the most desirable figure of merit and the one based on linear systolic array demonstrates the best scalability.作者: Vertebra 時(shí)間: 2025-4-1 04:26 作者: 碎石 時(shí)間: 2025-4-1 06:39
