標(biāo)題: Titlebook: Computational Intelligence in Digital and Network Designs and Applications; Mourad Fakhfakh,Esteban Tlelo-Cuautle,Patrick Siar Book 2015 S [打印本頁(yè)] 作者: 威風(fēng) 時(shí)間: 2025-3-21 16:32
書目名稱Computational Intelligence in Digital and Network Designs and Applications影響因子(影響力)
書目名稱Computational Intelligence in Digital and Network Designs and Applications影響因子(影響力)學(xué)科排名
書目名稱Computational Intelligence in Digital and Network Designs and Applications網(wǎng)絡(luò)公開(kāi)度
書目名稱Computational Intelligence in Digital and Network Designs and Applications網(wǎng)絡(luò)公開(kāi)度學(xué)科排名
書目名稱Computational Intelligence in Digital and Network Designs and Applications被引頻次
書目名稱Computational Intelligence in Digital and Network Designs and Applications被引頻次學(xué)科排名
書目名稱Computational Intelligence in Digital and Network Designs and Applications年度引用
書目名稱Computational Intelligence in Digital and Network Designs and Applications年度引用學(xué)科排名
書目名稱Computational Intelligence in Digital and Network Designs and Applications讀者反饋
書目名稱Computational Intelligence in Digital and Network Designs and Applications讀者反饋學(xué)科排名
作者: visceral-fat 時(shí)間: 2025-3-22 00:07 作者: 含沙射影 時(shí)間: 2025-3-22 04:25 作者: 鴕鳥 時(shí)間: 2025-3-22 05:50
https://doi.org/10.1007/978-3-319-20071-2Analog Mixed-Signal (AMS) Systems; Computational Intelligence (CI); Electronic Design; Evolutionary Alg作者: 不可接觸 時(shí)間: 2025-3-22 12:28 作者: 孤獨(dú)無(wú)助 時(shí)間: 2025-3-22 13:02
Iterative and Sequential Votingovide an undeniably attractive promise: The attained solution is the best available. In order to use convex optimization techniques, the target optimization problem must be modeled using convex functions. The gate sizing problem has been modeled in different ways to enable the use of convex optimiza作者: 孤獨(dú)無(wú)助 時(shí)間: 2025-3-22 17:11 作者: 節(jié)約 時(shí)間: 2025-3-23 00:48
Introduction to Asset Allocationdescribed, including techniques that take into account various technological parameters such as crosstalk. Such intelligent techniques guarantee that the integrated interconnections, used in power-managed SoCs, are well-designed, energy-optimal, and meet the performance objectives in all the SoCs op作者: narcissism 時(shí)間: 2025-3-23 02:39
https://doi.org/10.1007/978-3-319-89554-3owadays solved mainly using deterministic approaches. However, one of the main characteristics of these systems is the presence of uncertain data, such as the execution times of the tasks. The authors consider that the embedded systems design is one of the major domains for which applying optimizati作者: 軟弱 時(shí)間: 2025-3-23 09:17 作者: NOMAD 時(shí)間: 2025-3-23 12:18
Strategic and Tactical Asset Allocations after production. But this insertion of new elements itself may sometimes be a challenge, for bad choices could lead to unacceptable degradations of features of the circuit, while good choices may help reduce testing costs and circuit production costs. This chapter demonstrates how methods from Op作者: 以煙熏消毒 時(shí)間: 2025-3-23 17:40 作者: 諂媚于人 時(shí)間: 2025-3-23 19:11
https://doi.org/10.1007/978-3-658-20753-3ems become important when the circuit’s outputs are affected by its sensitive noisy inputs. In conventional circuits, the impact of the inputs on reliability can be observed by the deterministic input patterns. However, in nanoscale circuits, the inputs behave probabilistically. The Bayesian network作者: 沉著 時(shí)間: 2025-3-24 00:17
https://doi.org/10.1007/978-3-658-20753-3d low power consumption. In this chapter, we present a novel two-stage metaheuristic algorithm to optimize electrode interconnect routing for pin-constrained chips. The first stage models channel routing as a traveling salesman problem and solves it using the ant colony optimization algorithm. The s作者: 阻擋 時(shí)間: 2025-3-24 02:48
https://doi.org/10.1007/978-3-658-20753-3e charge-confined low-power optimum logic circuit design to enhance the computing performance of a novel nanotechnology architecture, the quantum dot cellular automata. We investigate robust and reliable diverse logic circuit design, such as hybrid adders and other binary adder schemes, among them b作者: finite 時(shí)間: 2025-3-24 09:24
https://doi.org/10.1007/978-3-658-20753-3ve several limitations—battery, low processing capabilities, among others—which often result in low diagnostic yield. In this chapter, after a technical presentation of the components of a standard WCE, the authors discuss the related limitations and introduce a new concept of smart capsule with emb作者: Preserve 時(shí)間: 2025-3-24 14:18 作者: 反復(fù)無(wú)常 時(shí)間: 2025-3-24 17:04 作者: 固定某物 時(shí)間: 2025-3-24 20:57
Design Intelligence for Interconnection Realization in Power-Managed SoCsdescribed, including techniques that take into account various technological parameters such as crosstalk. Such intelligent techniques guarantee that the integrated interconnections, used in power-managed SoCs, are well-designed, energy-optimal, and meet the performance objectives in all the SoCs operating states.作者: 男生如果明白 時(shí)間: 2025-3-24 23:28 作者: 教義 時(shí)間: 2025-3-25 05:24
Computational Intelligence in Digital and Network Designs and Applications978-3-319-20071-2作者: 音樂(lè)等 時(shí)間: 2025-3-25 07:46 作者: Migratory 時(shí)間: 2025-3-25 11:57
Regaining Truthfulness in Votingodologies. The Hardware Description Language specifications as well as the placement constraints can be automatically generated. A GUI-based CAD tool has been developed that is integrated with the Xilinx Integrated Software Environment for design automation of circuits from user specifications.作者: padding 時(shí)間: 2025-3-25 16:48
https://doi.org/10.1007/978-3-658-20753-3h potential advantages such as greater data storage, fast arithmetic operation, and the ability to solve nonbinary problems, will be important in multivalued computing, especially in the ternary computing paradigm.作者: 鐵砧 時(shí)間: 2025-3-25 22:52
A Fabric Component Based Approach to the Architecture and Design Automation of High-Performance Inteodologies. The Hardware Description Language specifications as well as the placement constraints can be automatically generated. A GUI-based CAD tool has been developed that is integrated with the Xilinx Integrated Software Environment for design automation of circuits from user specifications.作者: nautical 時(shí)間: 2025-3-26 01:10 作者: 兇兆 時(shí)間: 2025-3-26 04:55
Iterative and Sequential Votingtion techniques, such as linear programming and geometric programming. Statistical and robust sizing methods are included to reflect the importance of optimization techniques that are aware of variations. Applications of multi-objective optimization techniques that aid designers in evaluating the trade-offs are described.作者: harrow 時(shí)間: 2025-3-26 09:28
https://doi.org/10.1007/978-3-319-89554-3on under uncertainty is legitimate and highly beneficial. This chapter introduces the most suitable techniques from the field of optimization under uncertainty for the design of compilation chains and for the resolution of the associated optimization problems.作者: Solace 時(shí)間: 2025-3-26 13:45 作者: 震驚 時(shí)間: 2025-3-26 19:34 作者: 隱士 時(shí)間: 2025-3-26 21:48 作者: Criteria 時(shí)間: 2025-3-27 04:47
https://doi.org/10.1007/978-3-658-20753-3s technique is used to compute the reliability of a circuit in conjunction with the Monte Carlo simulations approach which is applied to model the probabilistic inputs and ultimately to determine sensitive inputs and worst-case input combinations.作者: ECG769 時(shí)間: 2025-3-27 08:46 作者: 某人 時(shí)間: 2025-3-27 11:23
https://doi.org/10.1007/978-3-658-20753-3edded image processing capabilities based on a boosting approach using textural features. We discuss the feasibility of the hardware integration of the detection–recognition method, also with respect to the most recent FPGA technologies.作者: ESO 時(shí)間: 2025-3-27 15:22
ing approaches and optimization techniques and their applica.This book explains the application of recent advances in computational intelligence – algorithms, design methodologies, and synthesis techniques – to the design of integrated circuits and systems. It highlights new biasing and sizing appro作者: 善于騙人 時(shí)間: 2025-3-27 18:39
Book 2015 the design of integrated circuits and systems. It highlights new biasing and sizing approaches and optimization techniques and their application to the design of high-performance digital, VLSI, radio-frequency, and mixed-signal circuits and systems..This second of two related volumes addresses digi作者: Immunotherapy 時(shí)間: 2025-3-27 23:38 作者: Working-Memory 時(shí)間: 2025-3-28 06:09 作者: SOW 時(shí)間: 2025-3-28 10:15
Digital IIR Filter Design with Fix-Point Representation Using Effective Evolutionary Local Search Ener, the universality of DE-based MA is improved by implementing more efficient evolutionary algorithms (EAs) as the local search techniques. The performance of the newly designed algorithm is experimentally verified in both function optimization tasks and digital IIR filter design problems.作者: 小木槌 時(shí)間: 2025-3-28 13:42
Applying Operations Research to Design for Test Insertion Problemserations Research—a scientific discipline rooted in both mathematics and computer science, leaning strongly on the formal modeling of optimization issues—help us adress such challenges and build efficient solutions leading to real-world solutions that may be integrated into electronic design software tools.作者: 墊子 時(shí)間: 2025-3-28 17:00 作者: 細(xì)絲 時(shí)間: 2025-3-28 19:58
The Impact of Sensitive Inputs on the Reliability of Nanoscale Circuitss technique is used to compute the reliability of a circuit in conjunction with the Monte Carlo simulations approach which is applied to model the probabilistic inputs and ultimately to determine sensitive inputs and worst-case input combinations.作者: Mucosa 時(shí)間: 2025-3-29 00:26
Pin-Count and Wire Length Optimization for Electrowetting-on-Dielectric Chips: A Metaheuristics-Baseecond stage provides detailed wire routes over a grid model. The algorithm is benchmarked over a set of real-life chip specifications. On average, comparing our results to previous work, we obtain reductions of approximately 39?% and 35?% on pin-count and total wire length, respectively.作者: 可商量 時(shí)間: 2025-3-29 06:34
Smart Videocapsule for Early Diagnosis of Colorectal Cancer: Toward Embedded Image Analysisedded image processing capabilities based on a boosting approach using textural features. We discuss the feasibility of the hardware integration of the detection–recognition method, also with respect to the most recent FPGA technologies.作者: 珊瑚 時(shí)間: 2025-3-29 10:57
Book 2015tal and network designs and applications, with 12 chapters grouped into parts on digital circuit design, network optimization, and applications. It will be of interest to practitioners and researchers in computer science and electronics engineering engaged with the design of electronic circuits..作者: expunge 時(shí)間: 2025-3-29 14:38 作者: mechanism 時(shí)間: 2025-3-29 19:23
