派博傳思國際中心

標(biāo)題: Titlebook: CMOS Data Converters for Communications; Mikael Gustavsson,J. Jacob Wikner,Nianxiong Nick T Book 2002 Springer Science+Business Media New [打印本頁]

作者: dejected    時間: 2025-3-21 17:07
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作者: 領(lǐng)巾    時間: 2025-3-21 23:06

作者: 一小塊    時間: 2025-3-22 03:58

作者: 蛙鳴聲    時間: 2025-3-22 07:23
Mikael Gustavsson,J. Jacob Wikner,Nianxiong Nick T
作者: 太空    時間: 2025-3-22 11:18

作者: consent    時間: 2025-3-22 16:17

作者: consent    時間: 2025-3-22 20:27
Springer Series in Materials Sciencem, we usually need to add 1~2 bit (or even more) design margin depending on the system trade-offs. Also coding can reduce the data converter requirements by 3~6 dB, which has not been treated in this chapter but can be easily added to the equations. As far as distortions are concerned, they usually
作者: 懲罰    時間: 2025-3-22 22:09
Pavel Topala,Vitalie Besliu,Laurentiu Marinrelation to the input signal and linearity errors in the multi-bit DAC will cause noise, not distortion. In addition to this the DAC linearity error is noise shaped, which significantly reduces the required linearity of the DAC. We have also discussed SC implementations of oversampled sigma-delta co
作者: 性行為放縱者    時間: 2025-3-23 03:30
Data Converter Requirements for Communications, requirements. In order to meet a communication system specification, we have derived minimum data converter requirements that are mostly influenced by the error probability and the peak-to-average ratio. We have also discussed optimum data converters for ADSL that are a function of application envi
作者: 跟隨    時間: 2025-3-23 06:16
Overview of D/A Converter Architectures,outlined some possible techniques for implementation, such as the charge-redistribution, current-steering, etc. As a guidance, we have summarized a number of reported performances of DACs that are suitable for higher-speed applications in an overviewing figure and table.
作者: Inferior    時間: 2025-3-23 11:05

作者: 影響    時間: 2025-3-23 15:16
Basic Analog Circuit Design,rs, and reference buffers. For high-performance SC data converters, the telescopic opamp with the SC CMFB is the recommended top choice since it is most power-efficient, least noisy, and fastest. To boost the gain, the gain-boosting technique is recommended. For voltage comparators, the best choice
作者: cocoon    時間: 2025-3-23 20:16
Time-Interleaved A/D Converters,be calibrated. A more severe problem is the phase skew errors which increases at high signal frequencies. The most effective way to reduce these errors is to use an input S/H circuit which usually needs an opamp that runs at the full speed of the ADC. The opamp is therefore difficult to design and p
作者: 愉快么    時間: 2025-3-23 22:40

作者: forestry    時間: 2025-3-24 06:23
Modeling of Nyquist D/A Converters,ructure, component sizes, etc., in current steering DACs. From the models, we can also calculate the effect of matching errors..Using the results in this chapter, we are able to simulate and predict the performance of the DAC on a high abstraction level, with for example Matlab, which saves time, ov
作者: Colonoscopy    時間: 2025-3-24 06:57
Implementation of CMOS Current-Steering D/A Converters,tlined and for high-speed and high-resolution applications we have found the segmented DAC structure to be most suitable. A key design issue is to find the proper number of bits encode into a thermometer code or if multi-segmented structures are needed. We have shown how the performance of the conve
作者: Commentary    時間: 2025-3-24 14:17

作者: Brittle    時間: 2025-3-24 17:46
Electron and Ion Microscopy Without Lensesoutlined some possible techniques for implementation, such as the charge-redistribution, current-steering, etc. As a guidance, we have summarized a number of reported performances of DACs that are suitable for higher-speed applications in an overviewing figure and table.
作者: laxative    時間: 2025-3-24 23:01

作者: SLING    時間: 2025-3-25 01:37
Electron and Ion Microscopy Without Lensesoutlined some possible techniques for implementation, such as the charge-redistribution, current-steering, etc. As a guidance, we have summarized a number of reported performances of DACs that are suitable for higher-speed applications in an overviewing figure and table.
作者: objection    時間: 2025-3-25 06:43

作者: Intentional    時間: 2025-3-25 08:37

作者: instate    時間: 2025-3-25 14:14
https://doi.org/10.1007/978-3-319-30198-3be calibrated. A more severe problem is the phase skew errors which increases at high signal frequencies. The most effective way to reduce these errors is to use an input S/H circuit which usually needs an opamp that runs at the full speed of the ADC. The opamp is therefore difficult to design and p
作者: 遵循的規(guī)范    時間: 2025-3-25 16:05
Pavel Topala,Vitalie Besliu,Laurentiu Marinmits the signal bandwidth. To increase the signal bandwidth cascaded modulators have been discussed. Gain errors in the integrators cause leakage of low order quantization noise at the output which limits the resolution of the converter. The integrator gain errors need not be as accurate as the full
作者: Seminar    時間: 2025-3-25 20:31
Ram Prasad,Busi Siddhardha,Madhu Dyavaiahructure, component sizes, etc., in current steering DACs. From the models, we can also calculate the effect of matching errors..Using the results in this chapter, we are able to simulate and predict the performance of the DAC on a high abstraction level, with for example Matlab, which saves time, ov
作者: 關(guān)心    時間: 2025-3-26 00:49
Pattnaik Subhaswaraj,Busi Siddhardhatlined and for high-speed and high-resolution applications we have found the segmented DAC structure to be most suitable. A key design issue is to find the proper number of bits encode into a thermometer code or if multi-segmented structures are needed. We have shown how the performance of the conve
作者: 激怒某人    時間: 2025-3-26 07:29

作者: Abominate    時間: 2025-3-26 10:55
https://doi.org/10.1007/b117690CMOS; Generator; analog; analog circuit design; communication; communication system; modeling
作者: FLING    時間: 2025-3-26 14:43
978-1-4419-4968-4Springer Science+Business Media New York 2002
作者: Invertebrate    時間: 2025-3-26 19:15
Overview of D/A Converter Architectures,outlined some possible techniques for implementation, such as the charge-redistribution, current-steering, etc. As a guidance, we have summarized a number of reported performances of DACs that are suitable for higher-speed applications in an overviewing figure and table.
作者: 下垂    時間: 2025-3-26 23:26

作者: Repetitions    時間: 2025-3-27 01:42

作者: amputation    時間: 2025-3-27 06:46
https://doi.org/10.1007/978-3-319-30198-3ower consuming. An improved global passive sampling technique that does not need an opamp was introduced. The limitations of the technique was also discussed. The phase skew distortion can be reduced by 10 to 20 dB compared to not using a global sampling technique.
作者: Cardiac-Output    時間: 2025-3-27 10:33
Ram Prasad,Busi Siddhardha,Madhu Dyavaiaher circuit-level simulations. Mostly, static requirements have been addressed but in the same results can be modified to cover AC as well..Extending the modeling, we can also use measured result from a DAC, and extract information on the process and the parasitic resistance and capacitance in the circuit.
作者: nettle    時間: 2025-3-27 16:49

作者: 通知    時間: 2025-3-27 21:31
Nanostructures and Quantum Effects data converter needs on-chip band-gap reference using the parasitic PNP transistors. With a high-accuracy voltage generated on-chip, we can derive an accurate current by resorting to an external precision resistor. To buffer the voltage reference for high performance data converters, we recommend a large external capacitor.
作者: aggressor    時間: 2025-3-28 00:51
Basic Analog Circuit Design, data converter needs on-chip band-gap reference using the parasitic PNP transistors. With a high-accuracy voltage generated on-chip, we can derive an accurate current by resorting to an external precision resistor. To buffer the voltage reference for high performance data converters, we recommend a large external capacitor.
作者: vitrectomy    時間: 2025-3-28 05:49

作者: ORBIT    時間: 2025-3-28 07:31

作者: COLIC    時間: 2025-3-28 10:48

作者: Heterodoxy    時間: 2025-3-28 15:11
Modeling of Nyquist D/A Converters,er circuit-level simulations. Mostly, static requirements have been addressed but in the same results can be modified to cover AC as well..Extending the modeling, we can also use measured result from a DAC, and extract information on the process and the parasitic resistance and capacitance in the circuit.
作者: senile-dementia    時間: 2025-3-28 21:50
Implementation of CMOS Current-Steering D/A Converters,rter depends on errors in the layout by comparing two similar DACs and highlighted the importance of high frequency poles in the output impedance of the unit current sources. We have shown that it is possible to reach an SFDR of over 75 dBc in a standard 3.3 V digital CMOS process and an SFDR of 65 dBc with a single 1.5-V supply voltage.
作者: 谷物    時間: 2025-3-29 01:20

作者: Entirety    時間: 2025-3-29 05:45

作者: 疾馳    時間: 2025-3-29 08:32
https://doi.org/10.1007/978-3-8350-9516-8s at stake in rival modes of global image banking. Despite continuities in service delivery, a profound difference of aesthetic allegiance separates Bettmann and Corbis–Bettmann, centered on the role of historicity in the manufacture of image banks.
作者: 繁榮中國    時間: 2025-3-29 12:29

作者: FECK    時間: 2025-3-29 18:02

作者: 愛好    時間: 2025-3-29 22:52
Howell G. M. Edwardso favor trapping of an electron, the detailed geometry of the trapping site can be changed by the presence of the electron. This is analogous to the solvation of an electron in which the surrounding molecular groups are reoriented by the presence of the electron compared to their orientation in the
作者: ELUDE    時間: 2025-3-30 01:09

作者: Polydipsia    時間: 2025-3-30 06:14
978-3-531-16759-6VS Verlag für Sozialwissenschaften | Springer Fachmedien Wiesbaden GmbH, Wiesbaden 2011
作者: 財主    時間: 2025-3-30 10:51

作者: 衰老    時間: 2025-3-30 14:17





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