標(biāo)題: Titlebook: Architecture of High Performance Computers; Volume I Uniprocesso R. N. Ibbett,N. P. Topham Book 1989 Roland N. Ibbett and Nigel P. Topham 1 [打印本頁] 作者: BROOD 時(shí)間: 2025-3-21 18:43
書目名稱Architecture of High Performance Computers影響因子(影響力)
書目名稱Architecture of High Performance Computers影響因子(影響力)學(xué)科排名
書目名稱Architecture of High Performance Computers網(wǎng)絡(luò)公開度
書目名稱Architecture of High Performance Computers網(wǎng)絡(luò)公開度學(xué)科排名
書目名稱Architecture of High Performance Computers被引頻次
書目名稱Architecture of High Performance Computers被引頻次學(xué)科排名
書目名稱Architecture of High Performance Computers年度引用
書目名稱Architecture of High Performance Computers年度引用學(xué)科排名
書目名稱Architecture of High Performance Computers讀者反饋
書目名稱Architecture of High Performance Computers讀者反饋學(xué)科排名
作者: –吃 時(shí)間: 2025-3-21 23:02 作者: MERIT 時(shí)間: 2025-3-22 02:59 作者: 富足女人 時(shí)間: 2025-3-22 08:09 作者: 支架 時(shí)間: 2025-3-22 10:03
Yannick Joye,Karolien Poels,Kim Willemslude instructions which implicitly process a sequence of vector elements. Computers with this latter facility have been described by Flynn [Fly72] as Single Instruction Multiple Data (SIMD) arrangements, in contrast with the Single Instruction Single Data (SISD) arrangement of conventional computers作者: seruting 時(shí)間: 2025-3-22 14:05
Evolutionary Quantitative Geneticsch is now produced commercially as the CYBER 205. In 1983 CDC formed a spin-off company, ETA Systems Inc., with the goal of producing a multiprocessor system (the ETA.), based on the CYBER 205 architecture and having a performance capability of 10 GigaFLOPS.作者: Focus-Words 時(shí)間: 2025-3-22 17:58 作者: Cytology 時(shí)間: 2025-3-22 21:51 作者: 酷熱 時(shí)間: 2025-3-23 01:41
Storage Hierarchies,echnology led to the need for more sophisticated systems and in this chapter we shall consider the virtual memory and paging systems used in Atlas, the cache stores used in some models in the IBM System/360 and System/370 ranges, and the MU5 storage hierarchy. Before discussing these systems in deta作者: Hla461 時(shí)間: 2025-3-23 06:06 作者: 不能強(qiáng)迫我 時(shí)間: 2025-3-23 10:56 作者: 典型 時(shí)間: 2025-3-23 14:14
The CRAY Series,lude instructions which implicitly process a sequence of vector elements. Computers with this latter facility have been described by Flynn [Fly72] as Single Instruction Multiple Data (SIMD) arrangements, in contrast with the Single Instruction Single Data (SISD) arrangement of conventional computers作者: 蓋他為秘密 時(shí)間: 2025-3-23 18:42
The CDC Series,ch is now produced commercially as the CYBER 205. In 1983 CDC formed a spin-off company, ETA Systems Inc., with the goal of producing a multiprocessor system (the ETA.), based on the CYBER 205 architecture and having a performance capability of 10 GigaFLOPS.作者: 聯(lián)想 時(shí)間: 2025-3-24 00:01
Performance of Vector Machines, is analysed it is useful to separate the architectural measurements from the technological measurements since this permits a comparison of the . of machines constructed from different technologies. This chapter therefore considers the ways in which the performance potential of vector processors can作者: epicardium 時(shí)間: 2025-3-24 03:30 作者: 撫慰 時(shí)間: 2025-3-24 09:08
Three Roads to Cultural RecurrenceIBM/360 architecture, used the term to “describe the attributes of a system as seen by the programmer, i.e. the conceptual structure and functional behaviour, as distinct from the organisation of the data flow and controls, the logical design and the physical implementation.” Stone [Sto75], on the o作者: 神經(jīng) 時(shí)間: 2025-3-24 10:52 作者: 序曲 時(shí)間: 2025-3-24 15:15
Three Roads to Cultural Recurrencey 1951 had a main store made up of eight Williams Tubes each containing 32 40-bit words and a drum backing store having a capacity of 3.75 Kwords. Initially users were required to organise their own store transfers between a selected drum track and a selected pair of Williams Tubes, but the Mark 1 A作者: Pamphlet 時(shí)間: 2025-3-24 23:05 作者: Judicious 時(shí)間: 2025-3-25 02:09
Postscript: The Virtues of Weak Modularity,n store accessing rate. This problem also impinges on instruction accessing, since for efficient operation instructions must also be supplied to the processor at a rate matching its execution rate. In the case of instruction accessing, however, the problem is ameliorated by the fact that most instru作者: 無關(guān)緊要 時(shí)間: 2025-3-25 03:51 作者: 包租車船 時(shí)間: 2025-3-25 11:23 作者: Detain 時(shí)間: 2025-3-25 13:13 作者: 增長 時(shí)間: 2025-3-25 16:53
Evolutionary Quantitative Geneticsfollow the progress of a separate line of development started by CDC in 1965 in response to a requirement of the Lawrence Livermore Laboratory for a vector processor capable of executing 100 MFLOPS. The machine which resulted was the STAR-100 [HT72]. A great deal of controversy raged about this mach作者: 治愈 時(shí)間: 2025-3-25 20:59 作者: OPINE 時(shí)間: 2025-3-26 02:07
https://doi.org/10.1007/978-1-4899-6712-1architecture; computer; performance; processor; Volume作者: Systemic 時(shí)間: 2025-3-26 06:35 作者: 委屈 時(shí)間: 2025-3-26 12:09
http://image.papertrans.cn/b/image/161322.jpg作者: insomnia 時(shí)間: 2025-3-26 16:25
Introduction,IBM/360 architecture, used the term to “describe the attributes of a system as seen by the programmer, i.e. the conceptual structure and functional behaviour, as distinct from the organisation of the data flow and controls, the logical design and the physical implementation.” Stone [Sto75], on the o作者: Fillet,Filet 時(shí)間: 2025-3-26 17:27 作者: Processes 時(shí)間: 2025-3-26 21:09 作者: 出汗 時(shí)間: 2025-3-27 02:40 作者: 發(fā)芽 時(shí)間: 2025-3-27 06:25
Instruction Buffers,n store accessing rate. This problem also impinges on instruction accessing, since for efficient operation instructions must also be supplied to the processor at a rate matching its execution rate. In the case of instruction accessing, however, the problem is ameliorated by the fact that most instru作者: Spinal-Fusion 時(shí)間: 2025-3-27 12:08
Parallel Functional Units,as a means of enhancing the performance of a processor at the top end of a range of general purpose computers. In the case of the CDC 6600, performance was the principal criterion of the design, and as we saw in chapter 2, the use of parallel functional units with an instruction set capable of explo作者: 不吉祥的女人 時(shí)間: 2025-3-27 14:55 作者: beta-carotene 時(shí)間: 2025-3-27 18:42
Vector Facilities in MU5,support in hardware for the management of data structures. Thus a data structure as seen by the programmer is broken up into small sections and mapped into the vector registers by software. In machines which process the programmer’s data structures more directly, a number of quite different problems作者: 為現(xiàn)場 時(shí)間: 2025-3-28 01:55 作者: thwart 時(shí)間: 2025-3-28 04:51
Performance of Vector Machines,d in memory, whereas the other, the CRAY family, uses operands held in vector registers. Knowledge about such aspects of their design, together with knowledge about the clock periods of these machines, provides a limited picture of their performance potential. For example, before spending several mi作者: CRACK 時(shí)間: 2025-3-28 10:17
https://doi.org/10.1007/978-94-007-2969-8the Scoreboard, the mechanism used to control the operation of these functional units. We shall then go on to consider some of the design modifications introduced in the CDC 7600, the successor to the 6600. Limitations inherent in the architectures of both the 6600 and 7600 led to the design of the CRAY-1, which we shall consider in chapter 7.作者: 巡回 時(shí)間: 2025-3-28 13:17
Parallel Functional Units,the Scoreboard, the mechanism used to control the operation of these functional units. We shall then go on to consider some of the design modifications introduced in the CDC 7600, the successor to the 6600. Limitations inherent in the architectures of both the 6600 and 7600 led to the design of the CRAY-1, which we shall consider in chapter 7.作者: 信徒 時(shí)間: 2025-3-28 16:02 作者: 胰島素 時(shí)間: 2025-3-28 19:16
Introduction,n be organised so as to maximise performance, as measured by, for example, average instruction execution time. Thus the architect of a high performance system seeks techniques whereby judicious use of increased cost and complexity in the hardware will give a significant increase in overall system performance.作者: 無法解釋 時(shí)間: 2025-3-29 02:52
9樓作者: 懶惰人民 時(shí)間: 2025-3-29 05:55
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10樓作者: 鋼筆記下懲罰 時(shí)間: 2025-3-29 14:53
10樓作者: 填料 時(shí)間: 2025-3-29 19:12
10樓
