標(biāo)題: Titlebook: Architecture of Computing Systems -- ARCS 2013; 26th International C Hana Kubátová,Christian Hochberger,Bernhard Sick Conference proceeding [打印本頁] 作者: TIBIA 時間: 2025-3-21 20:04
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書目名稱Architecture of Computing Systems -- ARCS 2013讀者反饋
書目名稱Architecture of Computing Systems -- ARCS 2013讀者反饋學(xué)科排名
作者: Sleep-Paralysis 時間: 2025-3-21 20:37
Power Monitoring for Mixed-Criticality on a Many-Core Platform,dence in terms of time and space, but also in terms of power consumption as the available energy for a many-core system has to be shared by all running applications. Increased power consumption of one application may reduce the available energy for other applications or the reliability and lifetime 作者: mydriatic 時間: 2025-3-22 04:19
On Confident Task-Accurate Performance Estimation,ate performance by simulating task-level models annotated with nominal execution time. In early design phases, source code, which is necessary for generating accurate annotations, is usually not available. Instead, extrapolated values or even estimated values are used for performance estimation, whi作者: 先驅(qū) 時間: 2025-3-22 04:37 作者: Fecundity 時間: 2025-3-22 08:48 作者: 定點 時間: 2025-3-22 14:05
A Multi-core Memory Organization for 3-D DRAM as Main Memory,s and reduce energy consumption in multicore systems. These new memory technologies present both opportunities and challenges to computer systems design..In this paper we address how such memories should be organized to fully benefit from these technologies. We propose to keep 3-D DRAMs as main memo作者: cruise 時間: 2025-3-22 18:29 作者: 山羊 時間: 2025-3-22 22:41
Virtual Register Renaming, a reorder buffer or physical registers for register renaming and instruction retirement. Instead, it uses a large number of virtual register IDs for register renaming, a physical register file of the same size as the logical register file, and checkpoints to bulk retire instructions and to recover 作者: 有偏見 時間: 2025-3-23 03:21
Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Causfrom both timing disturbances and interrupt overloads is presented. It is supposed that the software is driven by a real-time operating system and that the software is critical, so it is expected not to fail. The architecture is composed of an FPGA (MCU) utilized to run the hardware (software) part 作者: galley 時間: 2025-3-23 06:04 作者: 無彈性 時間: 2025-3-23 13:10
A Highly Dependable Self-adaptive Mixed-Signal Multi-core System-on-Chip,rtificial hormone system (AHS) as general control mechanism. The AHS is an implementation of a completely decentralized, self-organizing task allocation mechanism using self-X properties. To minimize the increase in complexity especially with respect to the analog parts, several different implementa作者: Valves 時間: 2025-3-23 17:00 作者: GULLY 時間: 2025-3-23 19:32
GALS-CMP: Chip-Multiprocessor for GALS Embedded Systems,ronous (GALS) formal model of computation. Programs are specified using the SystemJ concurrent programming language, suitable for modeling heterogeneous embedded applications that contain reactive and control driven parts and interact with the external environment. The proposed architecture is based作者: Aviary 時間: 2025-3-23 23:42
HW/SW Tradeoffs for Dynamic Message Scheduling in Controller Area Network (CAN),articipating computing nodes, which affect the usage of the communication bus. The concept of self-adaptivity of participating nodes plays an important role in reducing design effort while guaranteeing high system performance. The dynamic offset adaptation algorithm (DynOAA) for adaptive message sch作者: HEW 時間: 2025-3-24 04:54
A Data-Driven Approach for Executing the CG Method on Reconfigurable High-Performance Systems,dy the applicability of the Convey HC-1 for numerical applications by decomposing a preconditioned conjugate gradient (CG) method into several independent kernels that can operate concurrently. To allow overlapped execution and to minimize data transfers, we stream the data between the kernel units 作者: 太空 時間: 2025-3-24 10:21 作者: 曲解 時間: 2025-3-24 10:43
Profiling Energy Consumption of I/O Functions in Embedded Applications,pplication helps developers to understand the energy consumption of the software and to further optimize the energy efficiency of the designs. However, most of the existing energy profiling tools concentrate on the energy consumption analyses of processors and memory, and provide limited supports to作者: Glossy 時間: 2025-3-24 16:17
An Application-Aware Cache Replacement Policy for Last-Level Caches,cient cache replacement policies at LLC are essential for reducing the off-chip memory traffic as well as contention for memory bandwidth. Cache replacement techniques for unicore LLCs may not be efficient for multicore LLCs as multicore LLCs can be shared by applications with varying access behavio作者: Gum-Disease 時間: 2025-3-24 19:30
Deploying Hardware Locks to Improve Performance and Energy Efficiency of Hardware Transactional Memve to lock-based synchronization. Among the two most important alternatives proposed for conflict detection and data versioning in today’s Hardware Transactional Memory systems (HTMs), the .one allows increased concurrency, potentially bringing higher performance levels in most cases. Unfortunately,作者: capsule 時間: 2025-3-24 23:37 作者: 同步左右 時間: 2025-3-25 04:47
https://doi.org/10.1007/978-3-0348-8570-6estimation of the impact of thermal coupling in determining the appropriate status from a thermal stand-point. The presented approach is based on two stages: off-line characterization of the target architecture estimates thermal coupling coefficients, that will be used at run-time for proper DTM dec作者: 動脈 時間: 2025-3-25 10:21
Hyperbolic Equations of Nonscalar Typea was collected using an x86 ASIM-based performance simulator from Intel Labs. The data shows that the new architecture improves performance of a 2-wide out-of-order x86 processor core by an average of 4.2%, while saving 43% of the energy consumption of the reorder buffer and retirement register fil作者: 含糊 時間: 2025-3-25 15:09
Running Time Analysis: Switch Analysisplement concurrency, reactivity, and control flow in SystemJ. Experimental evaluation over a range of benchmarks shows significant performance improvements over the existing platforms developed for the execution of the SystemJ program.作者: 舊石器時代 時間: 2025-3-25 19:27
Algorithms for Intelligent Systemsficient utilization of the cache space. Experimental evaluation of ACR technique for 2-core and 4-core systems using SPEC CPU 2000 and 2006 benchmark suites shows significant speed-up improvement over the . and . techniques.作者: Harrowing 時間: 2025-3-25 22:12
Václav Větvi?ka Ph. D.,Petr ?íma Ph. D.ware brings important benefits in terms of execution time as well as energy consumption with respect to traditional commit protocols that use the general-purpose interconnection network . Additionally, our proposal has negligible requirements in terms of area. Results for a 16-core CMP show that the作者: 痛苦一下 時間: 2025-3-26 03:03
Exploiting Thermal Coupling Information in MPSoC Dynamic Thermal Management,estimation of the impact of thermal coupling in determining the appropriate status from a thermal stand-point. The presented approach is based on two stages: off-line characterization of the target architecture estimates thermal coupling coefficients, that will be used at run-time for proper DTM dec作者: Fresco 時間: 2025-3-26 04:53
Virtual Register Renaming,a was collected using an x86 ASIM-based performance simulator from Intel Labs. The data shows that the new architecture improves performance of a 2-wide out-of-order x86 processor core by an average of 4.2%, while saving 43% of the energy consumption of the reorder buffer and retirement register fil作者: expunge 時間: 2025-3-26 11:01
GALS-CMP: Chip-Multiprocessor for GALS Embedded Systems,plement concurrency, reactivity, and control flow in SystemJ. Experimental evaluation over a range of benchmarks shows significant performance improvements over the existing platforms developed for the execution of the SystemJ program.作者: landmark 時間: 2025-3-26 13:03 作者: 想象 時間: 2025-3-26 20:04
Deploying Hardware Locks to Improve Performance and Energy Efficiency of Hardware Transactional Memware brings important benefits in terms of execution time as well as energy consumption with respect to traditional commit protocols that use the general-purpose interconnection network . Additionally, our proposal has negligible requirements in terms of area. Results for a 16-core CMP show that the作者: 殘酷的地方 時間: 2025-3-26 21:04
https://doi.org/10.1007/978-981-13-5956-9tions are introduced. Besides the basics of the hormone controlled architecture, the paper presents the mapping onto a SoC, an evaluation of a completely simulated AHScontrolled SoC implementing the different approaches and validating the functionality, stability and upper timing boundaries and showing the improvements in system reliability.作者: LATE 時間: 2025-3-27 02:47
A Highly Dependable Self-adaptive Mixed-Signal Multi-core System-on-Chip,tions are introduced. Besides the basics of the hormone controlled architecture, the paper presents the mapping onto a SoC, an evaluation of a completely simulated AHScontrolled SoC implementing the different approaches and validating the functionality, stability and upper timing boundaries and showing the improvements in system reliability.作者: 合群 時間: 2025-3-27 09:10 作者: VOK 時間: 2025-3-27 12:59
Admissibility of Function Spacesg approaches. To measure the complexity of our proposed algorithm, a new metric, . is used. Our evaluation over scalable settings shows that an unstructured approach has a significant merit to solve scalability and fault-tolerance problems with lower message complexity over existing algorithms.作者: 浪費(fèi)時間 時間: 2025-3-27 15:49
Admissibility of Function Spaceson of mixed-critical applications running on a many-core platform. Isolating dynamic power consumption significantly reduces safety requirements for lower critical applications and therefore overall certification costs, making many-core systems more attractive for safety-critical applications.作者: Palpable 時間: 2025-3-27 18:42 作者: 浮雕寶石 時間: 2025-3-27 22:06
Further Applications and Complementso execute the requests. The performance evaluation shows that in gracious executions Iwazaru can perform around 30% faster than Castro and Liskov’s PBFT, which was previously used as an algorithm of choice for request ordering.作者: 談判 時間: 2025-3-28 02:33
Further Applications and Complementsry. The cache like addressing allows for fast address translation and better memory allocation among multiple processes. We explore a set of wide-ranging design parameters for page sizes, sub-page sizes, TLB sizes, and sizes of write-buffers.作者: 性別 時間: 2025-3-28 06:20 作者: RUPT 時間: 2025-3-28 11:12
https://doi.org/10.1007/978-981-32-9990-0full hardware implementation and a reconfigurable solution based on vendor tools. Our custom tool for the programming of the architecture performs considerably faster than using partial reconfiguration and the standard vendor tools and is smaller than a full hardware solution.作者: 謙卑 時間: 2025-3-28 17:06
An Unstructured Termination Detection Algorithm Using Gossip in Cloud Computing Environments,g approaches. To measure the complexity of our proposed algorithm, a new metric, . is used. Our evaluation over scalable settings shows that an unstructured approach has a significant merit to solve scalability and fault-tolerance problems with lower message complexity over existing algorithms.作者: 越自我 時間: 2025-3-28 20:45 作者: Hemiparesis 時間: 2025-3-29 00:12 作者: 侵略主義 時間: 2025-3-29 05:33
Iwazaru: The Byzantine Sequencer,o execute the requests. The performance evaluation shows that in gracious executions Iwazaru can perform around 30% faster than Castro and Liskov’s PBFT, which was previously used as an algorithm of choice for request ordering.作者: A簡潔的 時間: 2025-3-29 08:30
A Multi-core Memory Organization for 3-D DRAM as Main Memory,ry. The cache like addressing allows for fast address translation and better memory allocation among multiple processes. We explore a set of wide-ranging design parameters for page sizes, sub-page sizes, TLB sizes, and sizes of write-buffers.作者: 尊重 時間: 2025-3-29 13:33 作者: Immortal 時間: 2025-3-29 19:12
Custom Reconfigurable Architecture Based on Virtex 5 Lookup Tables,full hardware implementation and a reconfigurable solution based on vendor tools. Our custom tool for the programming of the architecture performs considerably faster than using partial reconfiguration and the standard vendor tools and is smaller than a full hardware solution.作者: DUST 時間: 2025-3-29 19:46 作者: 人工制品 時間: 2025-3-30 02:16
https://doi.org/10.1007/978-981-13-5956-9 instructions are fetched unnecessarily. This observation provides several opportunities to enhance GPUs. We discuss different possibilities and evaluate filter cache as a case study. Moreover, we investigate how variations in microarchitectural parameters impacts potential filter cache benefits in GPUs.作者: 偶然 時間: 2025-3-30 06:33
Inter-warp Instruction Temporal Locality in Deep-Multithreaded GPUs, instructions are fetched unnecessarily. This observation provides several opportunities to enhance GPUs. We discuss different possibilities and evaluate filter cache as a case study. Moreover, we investigate how variations in microarchitectural parameters impacts potential filter cache benefits in GPUs.作者: 不自然 時間: 2025-3-30 08:34
Conference proceedings 2013tical and practical results on self-organization, self-configuration, self-optimization, self-healing, and self-protection techniques, operating systems including but not limited to scheduling, memory management, power management, RTOS, energy-awareness, and green computing.作者: 消極詞匯 時間: 2025-3-30 13:07 作者: 大約冬季 時間: 2025-3-30 17:59 作者: 洞穴 時間: 2025-3-30 20:50
https://doi.org/10.1007/978-981-13-5956-9forming rapid system prototyping. Our design space exploration shows that both pure software and pure hardware implementations are possible. However, parts of the software implementation require a significant amount of computation. As a result a mixed HW/SW implementation is proposed.作者: LUDE 時間: 2025-3-31 01:56 作者: 肉體 時間: 2025-3-31 06:04
Algorithms for Intelligent Systemstwo typical I/O devices, i.e. WLAN and TFT-LCD, demonstrate that our proposed framework can provide accurate estimates on the energy consumption of I/O function calls and the errors between the estimation and measurement results are below 4%.作者: 招惹 時間: 2025-3-31 11:20
Synthetic Aperture Radar Data Processing on an FPGA Multi-core System,with 550?thousand logic cells and consumes about 10 watt. We apply software pipelining to hide memory latency and reduce the hardware footprint by 14%. We show that the system provides real-time processing of a SAR application that maps a 3000m wide area with a resolution of 2x2 meters.作者: 6Applepolish 時間: 2025-3-31 14:29 作者: 易受騙 時間: 2025-3-31 17:56 作者: 發(fā)出眩目光芒 時間: 2025-3-31 22:49
A Data-Driven Approach for Executing the CG Method on Reconfigurable High-Performance Systems,le-threaded software version on the HC-1 and up to 1.2 times compared to a 2-socket hex-core Intel Xeon Westmere system with 24 hardware threads for large problem sizes with only a single application engine.作者: 未開化 時間: 2025-4-1 03:56 作者: STING 時間: 2025-4-1 06:33 作者: Respond 時間: 2025-4-1 10:23
978-3-642-36423-5Springer-Verlag Berlin Heidelberg 2013作者: delegate 時間: 2025-4-1 15:51
Hana Kubátová,Christian Hochberger,Bernhard SickFast-track conference proceedings.State-of-the-art research.Up-to-date results作者: 得體 時間: 2025-4-1 19:06
Lecture Notes in Computer Sciencehttp://image.papertrans.cn/b/image/161314.jpg作者: Nonthreatening 時間: 2025-4-2 00:13
