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標題: Titlebook: Architecture of Computing Systems - ARCS 2017; 30th International C Jens Knoop,Wolfgang Karl,Thilo Pionteck Conference proceedings 2017 Spr [打印本頁]

作者: Chylomicron    時間: 2025-3-21 19:57
書目名稱Architecture of Computing Systems - ARCS 2017影響因子(影響力)




書目名稱Architecture of Computing Systems - ARCS 2017影響因子(影響力)學科排名




書目名稱Architecture of Computing Systems - ARCS 2017網(wǎng)絡公開度




書目名稱Architecture of Computing Systems - ARCS 2017網(wǎng)絡公開度學科排名




書目名稱Architecture of Computing Systems - ARCS 2017被引頻次




書目名稱Architecture of Computing Systems - ARCS 2017被引頻次學科排名




書目名稱Architecture of Computing Systems - ARCS 2017年度引用




書目名稱Architecture of Computing Systems - ARCS 2017年度引用學科排名




書目名稱Architecture of Computing Systems - ARCS 2017讀者反饋




書目名稱Architecture of Computing Systems - ARCS 2017讀者反饋學科排名





作者: FELON    時間: 2025-3-21 22:32

作者: 無關緊要    時間: 2025-3-22 00:34

作者: 豐富    時間: 2025-3-22 07:19

作者: Agility    時間: 2025-3-22 10:17

作者: 編輯才信任    時間: 2025-3-22 13:24

作者: CUB    時間: 2025-3-22 17:10

作者: 共和國    時間: 2025-3-22 23:59
0302-9743 missions. They were organized in topical sections entitled: resilience; accelerators; performance; memory systems; parallelism and many-core; scheduling; power/energy..978-3-319-54998-9978-3-319-54999-6Series ISSN 0302-9743 Series E-ISSN 1611-3349
作者: Minikin    時間: 2025-3-23 02:56

作者: 漂亮    時間: 2025-3-23 08:05

作者: 導師    時間: 2025-3-23 11:14

作者: 泥沼    時間: 2025-3-23 14:36

作者: 束以馬具    時間: 2025-3-23 19:10
Niko Beerenwinkel,Juliane Siebourgcy inside each phase. The results show the effectiveness of our proposed methodology in classifying phases with similar power behaviour. This information can be used by the system to control and maintain power bursts, increasing the data centre’s power efficiency by reducing the maximum-to-average power ratio.
作者: 收到    時間: 2025-3-23 22:23

作者: 破布    時間: 2025-3-24 04:25

作者: 歡樂東方    時間: 2025-3-24 10:24
OpenCL-Based 6D-Vision on Heterogeneous System on Chipserent optimizations in order to implement a high-performance calculation of a 6D field. Our 6D-Vision pipeline processes 24 frames per second and provides useful information about a traffic scene. Moreover, we have successfully integrated the design for a gesture control application.
作者: Ascribe    時間: 2025-3-24 12:21

作者: GLUE    時間: 2025-3-24 16:28
A Method for Fast Evaluation of Sharing Set Management Strategies in Cache Coherence Protocolsrdware cost, to help either choose an existing approach for a given application context, or evaluate new approaches. We demonstrate the applicability of our proposal by evaluating three existing scalable cache coherence protocols, obtaining results consistent with previous, low level, evaluations much more rapidly.
作者: 懦夫    時間: 2025-3-24 19:09
PLSS: A Scheduler for Multi-core Embedded Systemsd processors. To achieve our goal, we perform phase-wise offline profiling to guide the runtime task scheduling scheme. Our approach can improve performance of dual core system by upto 11% over . based scheduler (5% on average) and 35% over LLC . based approach (6.5% on average).
作者: ACME    時間: 2025-3-25 02:43

作者: 他姓手中拿著    時間: 2025-3-25 03:32
Fault-Tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support Hardware enhancements to further increase the applicability of the approach are proposed and evaluated with SPEC CPU 2006 benchmarks. The resulting performance overhead is 47% on average, assuming the existence of the proposed hardware support.
作者: 騷動    時間: 2025-3-25 08:27

作者: CLOT    時間: 2025-3-25 12:59

作者: Favorable    時間: 2025-3-25 16:57

作者: 沙漠    時間: 2025-3-25 22:30
Exploring ILP and TLP on a Polymorphic VLIW Processor can adapt its issue-width during runtime. By design, the processor can be perceived as a single wide core (8-issue VLIW) or two medium-wide cores (4-issue) or four small cores (2-issue) that can run high-ILP/low DLP, medium-ILP/medium DLP, and low-ILP/high-DLP applications, respectively. Furthermor
作者: 造反,叛亂    時間: 2025-3-26 01:17
https://doi.org/10.1007/978-1-4899-3487-1m the ground up having reliability as a major concern. Both operating systems were evaluated through extensive neutron-beam testings on a 28?nm ARM-based state-of-the-art system-on-chip, and their fault tolerance mechanisms reached reductions in the overall cross-sections relative to their baselines
作者: BUST    時間: 2025-3-26 05:13

作者: 莎草    時間: 2025-3-26 09:06

作者: 慢慢流出    時間: 2025-3-26 13:41

作者: 親屬    時間: 2025-3-26 17:46

作者: 幾何學家    時間: 2025-3-26 22:27
https://doi.org/10.1007/978-3-319-26467-7 can adapt its issue-width during runtime. By design, the processor can be perceived as a single wide core (8-issue VLIW) or two medium-wide cores (4-issue) or four small cores (2-issue) that can run high-ILP/low DLP, medium-ILP/medium DLP, and low-ILP/high-DLP applications, respectively. Furthermor
作者: 豐滿有漂亮    時間: 2025-3-27 01:20
Jens Knoop,Wolfgang Karl,Thilo PionteckIncludes supplementary material:
作者: 阻塞    時間: 2025-3-27 09:19
Lecture Notes in Computer Sciencehttp://image.papertrans.cn/b/image/161310.jpg
作者: Glycogen    時間: 2025-3-27 11:21

作者: 充滿裝飾    時間: 2025-3-27 16:05
978-3-319-54998-9Springer International Publishing AG 2017
作者: 必死    時間: 2025-3-27 21:04

作者: intoxicate    時間: 2025-3-27 22:15
https://doi.org/10.1007/978-1-4899-3487-1thod. Due to the shrinking of structures and operating voltages, these failures are increasingly becoming an issue even for terrestrial applications. Unfortunately, redundancy increases costs, area usage, and power consumption, which can hinder its utilization in cost- and power-sensitive safety-cri
作者: Coterminous    時間: 2025-3-28 04:29
Selection on the Protein-Coding Genomes. As an alternative to hardware-based lockstep solutions, software-based fault-tolerance mechanisms can increase the reliability of multi-core commercial-of-the-shelf (COTS) CPUs while being cheaper and more flexible. This paper proposes a software/hardware hybrid approach, which targets Intel’s cu
作者: macabre    時間: 2025-3-28 09:44
https://doi.org/10.1007/978-1-61779-585-5sion is computationally very expensive, hence most approaches rely on non-embedded hardware or even on hardware acceleration to enable a high-performance execution. This work considers 6D-Vision on a low-power heterogeneous System on Chip for the first time. Therefore, we present a powerful 6D-Visio
作者: anthropologist    時間: 2025-3-28 14:19
Julien Y. Dutheil,Asger Hobolthocus on the acceleration of sorting small sets of data with a maximum string length. In contrast, we propose an FPGA-accelerated architecture based on Radix-Trees, which has the ability to sort large sets of strings without practical limitation of the string length. The Radix-Tree is parameterizable
作者: 古文字學    時間: 2025-3-28 16:19

作者: 顛簸下上    時間: 2025-3-28 20:03

作者: 饑荒    時間: 2025-3-29 02:38

作者: ventilate    時間: 2025-3-29 05:45
https://doi.org/10.1007/978-1-4939-9074-0ads running on a single node, it is critical to achieve high memory bandwidth efficiency on large scale CMPs to support continued growth in the number CPU cores. In this paper, we present several mechanisms that improve the memory efficiency by improving the page hit rate for multi-core processors.
作者: 外星人    時間: 2025-3-29 07:14
Stéphane Aris-Brosou,Nicolas Rodrigue is again at stake. One seemingly simple issue is the management of the set of sharers of a memory block, but with that many processors, it is a major bottleneck in terms of hardware resources. In this paper, we define a high level simulation method to evaluate sharing set management strategies, usi
作者: 符合國情    時間: 2025-3-29 14:37
Detecting Laterally Transferred Genesemory systems that combine faster 3D-DRAMs, DDRx DRAM and non-volatile memories (NVMs). In this paper we evaluate prefetching in a flat-addressable heterogeneous memory comprising High Bandwidth Memory (HBM) and phase change memory (PCM). We find that large prefetch buffers (64?MB) can outperform sm
作者: blister    時間: 2025-3-29 18:38
Niko Beerenwinkel,Juliane Siebourgared memory interference is a major source of pessimism in many-core systems, fine-grained message passing between small cores with private memories is used instead of a global shared memory..In this paper, the RC/MC architecture is presented and evaluated by three models: a VHDL model that can be u
作者: 上腭    時間: 2025-3-29 19:55
Evolutionary Gerontology and Geriatricsd multi/many-processor systems-on-chip (MPSoCs) to general-purpose chip multiprocessors (CMPs). A common aspect in almost all NoC workloads is the varying size of data transmitted by each transaction: while large data blocks are transferred as multiple-flit packets, a part of the traffic consists of
作者: 強制令    時間: 2025-3-30 00:44

作者: Synapse    時間: 2025-3-30 05:23
https://doi.org/10.1007/978-3-319-26467-7such workloads. However, they suffer from the fact that any mismatch between the application’s inherent instruction-level parallelism (ILP) and the core’s parallelism leads to unused resources or loss in performance. An accepted solution is to include several types of cores and match them dynamicall
作者: Legion    時間: 2025-3-30 11:23
Conference proceedings 2017n April 2017. .The 19 full papers presented in this volume were carefully reviewed and selected from 42 submissions. They were organized in topical sections entitled: resilience; accelerators; performance; memory systems; parallelism and many-core; scheduling; power/energy..
作者: Glucose    時間: 2025-3-30 13:13
Effectiveness of Software-Based Hardening for Radiation-Induced Soft Errors in Real-Time Operating Sthod. Due to the shrinking of structures and operating voltages, these failures are increasingly becoming an issue even for terrestrial applications. Unfortunately, redundancy increases costs, area usage, and power consumption, which can hinder its utilization in cost- and power-sensitive safety-cri
作者: 多產(chǎn)子    時間: 2025-3-30 18:02

作者: TIA742    時間: 2025-3-30 21:41
OpenCL-Based 6D-Vision on Heterogeneous System on Chipssion is computationally very expensive, hence most approaches rely on non-embedded hardware or even on hardware acceleration to enable a high-performance execution. This work considers 6D-Vision on a low-power heterogeneous System on Chip for the first time. Therefore, we present a powerful 6D-Visio
作者: 半球    時間: 2025-3-31 03:00
Hardware-Accelerated Radix-Tree Based String Sorting for Big Data Applicationsocus on the acceleration of sorting small sets of data with a maximum string length. In contrast, we propose an FPGA-accelerated architecture based on Radix-Trees, which has the ability to sort large sets of strings without practical limitation of the string length. The Radix-Tree is parameterizable
作者: 方便    時間: 2025-3-31 05:53
Boosting Java Performance Using GPGPUsdevelopers to benefit from using heterogeneous hardware whilst minimizing the amount of code refactoring required. Jacc utilizes two key abstractions: . which encapsulate all the information needed to execute code on a GPGPU; and . which capture both inter-task control-flow and data dependencies. Th
作者: CLAP    時間: 2025-3-31 12:47





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