標(biāo)題: Titlebook: Architecture of Computing Systems - ARCS 2011; 24th International C Mladen Berekovic,William Fornaciari,Cristina Silva Conference proceedin [打印本頁] 作者: 萬能 時間: 2025-3-21 17:21
書目名稱Architecture of Computing Systems - ARCS 2011影響因子(影響力)
書目名稱Architecture of Computing Systems - ARCS 2011影響因子(影響力)學(xué)科排名
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書目名稱Architecture of Computing Systems - ARCS 2011網(wǎng)絡(luò)公開度學(xué)科排名
書目名稱Architecture of Computing Systems - ARCS 2011被引頻次
書目名稱Architecture of Computing Systems - ARCS 2011被引頻次學(xué)科排名
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書目名稱Architecture of Computing Systems - ARCS 2011年度引用學(xué)科排名
書目名稱Architecture of Computing Systems - ARCS 2011讀者反饋
書目名稱Architecture of Computing Systems - ARCS 2011讀者反饋學(xué)科排名
作者: 分發(fā) 時間: 2025-3-21 21:45 作者: 最高點 時間: 2025-3-22 02:52 作者: 危機 時間: 2025-3-22 07:58
https://doi.org/10.1007/978-3-319-11322-7and the host system do not share a common memory. Sourcing out the data to the additional hardware thus introduces a communication penalty. Based on a combination of a program’s source code and execution profiling we perform an analysis which evaluates the arithmetic intensity as a cost function to 作者: 異端邪說2 時間: 2025-3-22 11:20
https://doi.org/10.1007/978-3-319-11322-7essor architecture, taking into consideration critical parameters such as cache bandwidth and memory latency. We compare the performance of 256 Polymorphic Register File-augmented workers against a single Cell PowerPC Processor Unit (PPU). In such a scenario, simulation results suggest that for the 作者: Vital-Signs 時間: 2025-3-22 14:34 作者: TOXIC 時間: 2025-3-22 19:13
https://doi.org/10.1007/978-1-349-00271-9 and power analysis of general purpose many-core chips using this law, we carry out an analysis aiming at many-core SoCs integrating processors sharing the same core instruction set but each potentially having additional extensions. For SoCs targeting well defined classes of applications, higher per作者: bromide 時間: 2025-3-22 22:13 作者: 先行 時間: 2025-3-23 03:59 作者: exclamation 時間: 2025-3-23 06:13 作者: osteocytes 時間: 2025-3-23 12:55
https://doi.org/10.1057/9780230502192rchitecture is based on a layer concept that provides important advantages for its flexibility. This makes it possible to reconfigure and automatically generate the test system determined by the board’s properties and the specific test algorithms. The principal system components are a soft-processor作者: 割讓 時間: 2025-3-23 13:56
Evolutionary Foundations of Economic Scienceeople who live, work or socialise in these environments. To achieve this level of intelligence, such environments collect, store, represent and interpret a vast amount of information which describe the current context of its users. The aim of this research is to develop a generic and extensible arch作者: Celiac-Plexus 時間: 2025-3-23 21:42
https://doi.org/10.1007/978-4-431-54844-7of threads in a single-core configuration of the UTLEON3 processor that implements the SVP microthreading model. The analysis is supported by code execution in an FPGA implementation of the processor..By classifying long-latency operations as either . (e.g. floating-point operations) or . (e.g. cach作者: harangue 時間: 2025-3-24 01:19 作者: TIGER 時間: 2025-3-24 03:19
https://doi.org/10.1007/978-1-4471-2179-4ry and insert it into the cache such that overall performance is increased. Modern memory controllers reorder memory requests to exploit the 3D structure of modern DRAM interfaces. In particular, prioritizing memory requests that use open pages increases throughput significantly. In this work, we in作者: Anticoagulant 時間: 2025-3-24 07:42 作者: 緯度 時間: 2025-3-24 11:45
https://doi.org/10.1007/978-3-642-30117-9ore they are needed, they introduce a large latency overhead for computations with unpredictable access behavior. Software caches are advantageous when the data set is not predictable but exhibits locality. However, software caches also incur a large overhead. Because the main overhead is in the acc作者: 利用 時間: 2025-3-24 18:13
Other Games on Static Complex Networksity, thus resulting in a larger number of cores on the chip. This, in turn, places pressure on the off-chip and pin bandwidth. Large Last-Level Caches (LLC), which are shared among all cores, have been used as a way to control the out-of-chip requests..In this work we focus on analyzing the memory b作者: 怎樣才咆哮 時間: 2025-3-24 21:58 作者: 來這真柔軟 時間: 2025-3-25 01:35
Evolutionary Games in Complex Topologiest is not feasible to observe large surveillance areas using stationary cameras. This drawback can be overcome by using active vision (AcVi) systems consisting of mobile cameras (called AcVi nodes), which are reconfigurable in both position and orientation. In case of a dynamic environment with movin作者: Entrancing 時間: 2025-3-25 07:20 作者: Medicaid 時間: 2025-3-25 08:54 作者: 仲裁者 時間: 2025-3-25 13:02 作者: Duodenitis 時間: 2025-3-25 19:24 作者: Minuet 時間: 2025-3-25 21:44 作者: Ancestor 時間: 2025-3-26 02:11
Alejandro Casas,Fabiola Parra,José Blancason-aware power saving enables power saving in such systems subject to SLAs. In our experimental evaluations using industrial standard benchmark TPC-C and real server workloads, 7.6% of total power consumption was saved. This reduction corresponds to 1000kJ a day in a typical entry level server.作者: 淡紫色花 時間: 2025-3-26 07:02 作者: Myofibrils 時間: 2025-3-26 10:41
https://doi.org/10.1007/978-1-4471-2179-4ons. To avoid this problem, we propose a novel prefetch scheduling heuristic called . that selectively prioritizes prefetches to open DRAM pages such that performance regressions are minimized. Opportunistic prefetch scheduling reduces performance regressions by 6.7X and 5.2X, while improving perfor作者: 大喘氣 時間: 2025-3-26 15:12
Other Games on Static Complex Networkse most power efficient. If on the other hand, memory latency is the dominant factor, assuming bandwidth is not a limitation, then the best configuration is the one with more clusters and smaller LLCs.作者: 減震 時間: 2025-3-26 18:19 作者: 英寸 時間: 2025-3-26 21:43 作者: WATER 時間: 2025-3-27 03:21 作者: mighty 時間: 2025-3-27 07:07 作者: 退潮 時間: 2025-3-27 11:43
Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3 can be used to optimize code compilation for the microthreaded processor. As the compiler specifies the blocksize parameter for each family of threads individually, it can optimize the register file utilization of the processor.作者: kindred 時間: 2025-3-27 15:53
Exploring the Prefetcher/Memory Controller Design Space: An Opportunistic Prefetch Scheduling Strateons. To avoid this problem, we propose a novel prefetch scheduling heuristic called . that selectively prioritizes prefetches to open DRAM pages such that performance regressions are minimized. Opportunistic prefetch scheduling reduces performance regressions by 6.7X and 5.2X, while improving perfor作者: milligram 時間: 2025-3-27 21:44 作者: obnoxious 時間: 2025-3-27 22:29
A Light-Weight Approach for Online State Classification of Self-organizing Parallel Systemsm the information provided by a dedicated, distributed monitoring infrastructure. An important feature of this approach is its capability to self-adapt, i.e., the monitoring infrastructure can adapt the rules to react to given requirements and/or changed system behavior. The proposed method is light作者: FRONT 時間: 2025-3-28 04:21 作者: BACLE 時間: 2025-3-28 09:50
A Code-Based Analytical Approach for Using Separate Device Coprocessors in Computing Systemsand the host system do not share a common memory. Sourcing out the data to the additional hardware thus introduces a communication penalty. Based on a combination of a program’s source code and execution profiling we perform an analysis which evaluates the arithmetic intensity as a cost function to 作者: dandruff 時間: 2025-3-28 12:58
Scalability Evaluation of a Polymorphic Register File: A CG Case Studyessor architecture, taking into consideration critical parameters such as cache bandwidth and memory latency. We compare the performance of 256 Polymorphic Register File-augmented workers against a single Cell PowerPC Processor Unit (PPU). In such a scenario, simulation results suggest that for the 作者: Apogee 時間: 2025-3-28 17:03
Experiences with String Matching on the Fermi Architecturepaper we present an efficient implementation of the Aho-Corasick string matching algorithm on Graphic Processing Units (GPUs), showing how we progressively redesigned the algorithm and the data structures to fit on the architecture. We then evaluate the implementation on single and multiple Tesla C2作者: superfluous 時間: 2025-3-28 21:01 作者: Hyperopia 時間: 2025-3-29 01:00
Application-Aware Power Saving for Online Transaction Processing Using Dynamic Voltage and Frequencyservers, power saving of an online transaction processing (OLTP) systems, which are major applications in data centers, is important. The OLTP system consumes relatively large amount of power because it is often equipped with a lot of computing and storage resources. Its power saving is difficult be作者: 收養(yǎng) 時間: 2025-3-29 04:50
Frameworks for Multi-core Architectures: A Comprehensive Evaluation Using 2D/3D Image Registrationes onto one chip. This changed also the way programs are written in order to leverage the processing power of multiple cores of the same processor. In the beginning, programmers had to divide and distribute the work by hand to the available cores and to manage threads in order to use more than one c作者: IDEAS 時間: 2025-3-29 10:35
Emulating Transactional Memory on FPGA Multiprocessors We introduce two systems, integrating only off-the-shelf components, that respectively use a centralized and a distributed approach, presenting their hardware and software design. We analyze and compare these two architectures to a lock based multiprocessor prototype, discussing the trade-offs in t作者: 鑲嵌細(xì)工 時間: 2025-3-29 12:11 作者: Ligament 時間: 2025-3-29 18:12 作者: COMA 時間: 2025-3-29 20:49 作者: conservative 時間: 2025-3-30 03:20
A Dynamic Instruction Scratchpad Memory for Embedded Processors Managed by Hardwarehat every instruction will be fetched from the local, fast and timing predictable scratchpad memory. Thus, a predictable behavior is reached that eases a precise timing analysis of the system. We estimate the hardware resources required to implement the dynamic instruction scratchpad for an FPGA. An作者: 實施生效 時間: 2025-3-30 05:42 作者: 反叛者 時間: 2025-3-30 11:55
Compiler-Assisted Selection of a Software Transactional Memory System of an STM system at compile time. The performance of the application depends on choosing the right parameters. Unfortunately, programmers do not always know the application characteristic to decide on a profound basis. As a consequence, the application may run longer than necessary. Thus, we propos作者: cipher 時間: 2025-3-30 14:25 作者: PAN 時間: 2025-3-30 17:53 作者: Abrupt 時間: 2025-3-31 00:21 作者: 向外才掩飾 時間: 2025-3-31 03:54 作者: modish 時間: 2025-3-31 07:45 作者: corn732 時間: 2025-3-31 11:59 作者: 雜色 時間: 2025-3-31 13:22
Conference proceedings 2011The papers are organized in topical sections on customization and application specific accelerators; multi/many-core architectures; adaptive system architectures; processor architectures; memory architectures optimization; organic and autonomic computing; network-on-chip architectures.作者: FLIC 時間: 2025-3-31 18:14
https://doi.org/10.1007/978-3-319-11322-7identify those parts most reasonable to source out to the accelerating hardware. The basic principles of this analysis are introduced and tested with a sample application. Its concrete results are discussed and evaluated based on the performance of a FPGA-based and a GPU-based implementation.作者: Sleep-Paralysis 時間: 2025-4-1 01:43
Seeing in an Evolutionary Perspective,050 (T20 “Fermi” based) boards, comparing them to the previous Tesla C1060 (T10 based) solutions and equivalent multi-core implementations on x86 CPUs. We discuss the various tradeoffs of the different architectures.作者: Tincture 時間: 2025-4-1 04:50 作者: Invigorate 時間: 2025-4-1 06:05
https://doi.org/10.1007/978-1-4614-0712-6 evaluation quantifies the impact of our scratchpad on average case performance. It shows that the dynamic instruction scratchpad compared to standard instruction memories has a reasonable performance - while providing predictable behavior and easing timing analysis.作者: Condense 時間: 2025-4-1 12:45
A Code-Based Analytical Approach for Using Separate Device Coprocessors in Computing Systemsidentify those parts most reasonable to source out to the accelerating hardware. The basic principles of this analysis are introduced and tested with a sample application. Its concrete results are discussed and evaluated based on the performance of a FPGA-based and a GPU-based implementation.作者: Excitotoxin 時間: 2025-4-1 14:27 作者: Arctic 時間: 2025-4-1 18:30
