標(biāo)題: Titlebook: Architecture of Computing Systems; 36th International C Georgios Goumas,Sven Tomforde,Thilo Pionteck Conference proceedings 2023 The Editor [打印本頁(yè)] 作者: panache 時(shí)間: 2025-3-21 19:36
書目名稱Architecture of Computing Systems影響因子(影響力)
書目名稱Architecture of Computing Systems影響因子(影響力)學(xué)科排名
書目名稱Architecture of Computing Systems網(wǎng)絡(luò)公開度
書目名稱Architecture of Computing Systems網(wǎng)絡(luò)公開度學(xué)科排名
書目名稱Architecture of Computing Systems被引頻次
書目名稱Architecture of Computing Systems被引頻次學(xué)科排名
書目名稱Architecture of Computing Systems年度引用
書目名稱Architecture of Computing Systems年度引用學(xué)科排名
書目名稱Architecture of Computing Systems讀者反饋
書目名稱Architecture of Computing Systems讀者反饋學(xué)科排名
作者: 史前 時(shí)間: 2025-3-21 21:27
Yanan Sun,Gary G. Yen,Mengjie Zhanginto appropriate quadrants . and . or . and ., adjacent 2-bit errors can be corrected. Up to 2-bit check bit errors are detected as well as all burst errors shorter than the side length of the data array. Correct check bits can be recomputed from the corrected data bits. The correction is as fast as for an unmodified cross-parity code.作者: BROOK 時(shí)間: 2025-3-22 02:16
Evolutionary Design and Manufacturevert an . to a hardware specific ADNA, knowledge about how to calculate a required sensor value that cannot be directly measured by the hardware from other available sensors is required. In this paper, we present and analyze two algorithms that determine this knowledge.作者: 祖先 時(shí)間: 2025-3-22 04:38
Modified Cross Parity Codes for?Adjacent Double Error Correctioninto appropriate quadrants . and . or . and ., adjacent 2-bit errors can be corrected. Up to 2-bit check bit errors are detected as well as all burst errors shorter than the side length of the data array. Correct check bits can be recomputed from the corrected data bits. The correction is as fast as for an unmodified cross-parity code.作者: output 時(shí)間: 2025-3-22 12:45 作者: Magisterial 時(shí)間: 2025-3-22 13:56 作者: Palatial 時(shí)間: 2025-3-22 20:07
Energy Efficient LSTM Accelerators for?Embedded FPGAs Through Parameterised Architecture Designed to different situations using a number of optimisation parameters, such as the usage of DSPs or the implementation of activation functions. We present our key design decisions and evaluate the performance. Our accelerator achieves an energy efficiency of 11.89 GOP/s/W during a real-time inference with 32873 samples/s.作者: Expand 時(shí)間: 2025-3-23 00:47 作者: Bricklayer 時(shí)間: 2025-3-23 04:03 作者: Postmenopause 時(shí)間: 2025-3-23 05:45
: Investigating Total Store Ordering on?ARMrocessor architecture. Based on various workloads, our findings indicate that TSO is, on average, 8.94% slower than ARM’s weaker memory ordering. Through synthetic benchmarks, we further explore the workloads that experience the most significant performance degradation due to TSO.作者: 使饑餓 時(shí)間: 2025-3-23 11:29
Retrofitting AMD x86 Processors with?Active Virtual Machine Introspection Capabilitiesssumptions about active introspection mechanisms in previous work, offer constructions for solution strategies on . systems and discuss stealthiness and correctness. Finally, we show empirically that such retrofitted software solutions exhibit performance metrics in the same order of magnitude as native hardware solutions.作者: 領(lǐng)導(dǎo)權(quán) 時(shí)間: 2025-3-23 17:12 作者: Fantasy 時(shí)間: 2025-3-23 21:22
Global Induction of Univariate Treess approaches such as adaptive diagnostics employing neural networks for fault detection and localization, adaptive probing for fault identification, and strategies for degraded performance states and system reconfiguration to circumvent complete service disruption when computational resources are insufficient.作者: PAD416 時(shí)間: 2025-3-24 00:26
Self-adaptive Diagnosis and?Reconfiguration in?ADNA-Based Organic Computings approaches such as adaptive diagnostics employing neural networks for fault detection and localization, adaptive probing for fault identification, and strategies for degraded performance states and system reconfiguration to circumvent complete service disruption when computational resources are insufficient.作者: ingenue 時(shí)間: 2025-3-24 05:22
Evolutionary Criminology and Cooperationed to different situations using a number of optimisation parameters, such as the usage of DSPs or the implementation of activation functions. We present our key design decisions and evaluate the performance. Our accelerator achieves an energy efficiency of 11.89 GOP/s/W during a real-time inference with 32873 samples/s.作者: Ledger 時(shí)間: 2025-3-24 09:06
Oblique and Mixed Decision Trees to assess if it is still able to function after a component breaks, as well as to plan maintenance or repair actions, which will most likely involve human repair workers. Within this work, three different approaches on how to prioritize such maintenance actions within the scope of an Organic Computing system are presented and evaluated.作者: 聾子 時(shí)間: 2025-3-24 13:19
Yanan Sun,Gary G. Yen,Mengjie Zhangovide insights into improving bus utilization and bandwidth and reducing stalls in the system. The paper proposes hardware/software (HW/SW) advancements to reach and use the HBM device with a higher percentage than 80% at the memory controllers in the simulated manycore system.作者: Mri485 時(shí)間: 2025-3-24 18:38 作者: 顛簸地移動(dòng) 時(shí)間: 2025-3-24 23:02
J. C. W. Sullivan,B. Carse,A. G. Pipessumptions about active introspection mechanisms in previous work, offer constructions for solution strategies on . systems and discuss stealthiness and correctness. Finally, we show empirically that such retrofitted software solutions exhibit performance metrics in the same order of magnitude as native hardware solutions.作者: Extort 時(shí)間: 2025-3-25 02:01
0302-9743 e in Athens, Greece, in June 2023..The 18 full papers in this volume were carefully reviewed and selected from 35 submissions..ARCS provides a platform covering newly emerging and cross-cutting topics, such as autonomous and ubiquitous systems, reconfigurable computing and acceleration, neural netwo作者: 焦慮 時(shí)間: 2025-3-25 04:12
Parallel and Distributed Computation we experimentally investigate an existing approach of a steganographic channel in a transmission with error correction code with respect to bandwidth, robustness and detectability, and expand this construction to provide another example of multi-level steganography, i.e., a steganographic channel within a steganographic channel.作者: palliate 時(shí)間: 2025-3-25 11:03
Error Codes in?and?for?Network Steganography we experimentally investigate an existing approach of a steganographic channel in a transmission with error correction code with respect to bandwidth, robustness and detectability, and expand this construction to provide another example of multi-level steganography, i.e., a steganographic channel within a steganographic channel.作者: BADGE 時(shí)間: 2025-3-25 12:29
A Comparative Study of Neural Network Compilers on ARMv8 Architecturerameworks that target (mainly) far edge devices: TensorFlow Lite for MCUs, GLOW, and IREE. For a fair comparison, our performance analysis targets to reveal the performance benefits offered by the different optimization levels for the three studied frameworks as well as the strength of specific grap作者: Anthem 時(shí)間: 2025-3-25 17:42
Predicting Physical Disturbances in?Organic Computing Systems Using Automated Machine Learningor learning to predict physical disturbances in an iterative manner. We evaluate our approach using a freely available dataset from the broader domain of Predictive Maintenance research and show that our approach is able to build predictors with reasonable prediction quality autonomously.作者: Judicious 時(shí)間: 2025-3-25 22:12 作者: 繁忙 時(shí)間: 2025-3-26 02:03
Back to?the?Core-Memory Age: Running Operating Systems in?NVRAM only and 56 cores total, we also observed a reduction in power draw in several scenarios. Due to prolonged execution times, the energy consumption increased as well for these measured workloads. While this might be discouraging at first sight, this result was achieved . performance tuning as to the spec作者: Choreography 時(shí)間: 2025-3-26 05:01
Dao Vu Truong Son,Pham Nhat Tanrameworks that target (mainly) far edge devices: TensorFlow Lite for MCUs, GLOW, and IREE. For a fair comparison, our performance analysis targets to reveal the performance benefits offered by the different optimization levels for the three studied frameworks as well as the strength of specific grap作者: 有限 時(shí)間: 2025-3-26 09:43 作者: 是貪求 時(shí)間: 2025-3-26 13:34 作者: ADORE 時(shí)間: 2025-3-26 20:30
Evolutionary Design and Manufacture and 56 cores total, we also observed a reduction in power draw in several scenarios. Due to prolonged execution times, the energy consumption increased as well for these measured workloads. While this might be discouraging at first sight, this result was achieved . performance tuning as to the spec作者: effrontery 時(shí)間: 2025-3-26 21:18
https://doi.org/10.1007/978-3-031-42785-5computer hardware; distributed computer systems; distributed systems; embedded systems; field programmab作者: MITE 時(shí)間: 2025-3-27 05:01
978-3-031-42784-8The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerl作者: BAIT 時(shí)間: 2025-3-27 05:19
Architecture of Computing Systems978-3-031-42785-5Series ISSN 0302-9743 Series E-ISSN 1611-3349 作者: GOAT 時(shí)間: 2025-3-27 10:24
Lecture Notes in Computer Sciencehttp://image.papertrans.cn/b/image/161304.jpg作者: CUB 時(shí)間: 2025-3-27 17:32
Evolutionary Criminology and Cooperation embedded devices. In this paper, we propose a new hardware accelerator design for LSTMs specially optimised for resource-scarce embedded Field Programmable Gate Arrays (FPGAs). Our design improves the execution speed and reduces energy consumption compared to related work. Moreover, it can be adapt作者: interpose 時(shí)間: 2025-3-27 19:23 作者: poliosis 時(shí)間: 2025-3-28 01:58
Oblique and Mixed Decision Treeso interact with their surrounding environment. As any kind of physical hardware component, such sensors and actuators will fail after a usually unknown amount of time. Besides the obvious task of identifying or predicting hardware failures, an Organic Computing system will furthermore be responsible作者: 期滿 時(shí)間: 2025-3-28 04:06
https://doi.org/10.1007/978-3-030-21851-5disturbances, therefore, failures or breakdowns that affect a systems physical components. Before experiencing such a disturbance, physical components may show various measurable signs of deterioration that might be assessed through sensor data. If interpreted correctly, it would be possible to pred作者: 蜿蜒而流 時(shí)間: 2025-3-28 07:03
Global Induction of Univariate Treeswhere safety is paramount and system operability must persist despite faults or failures. The implementation of Organic Computing offers substantial benefits to these intricate, dynamic systems, such as decreased development effort, enhanced adaptability, and resilience. Nonetheless, safety-critical作者: Finasteride 時(shí)間: 2025-3-28 13:47
Parallel and Distributed Computationre used in steganographic channels and examples where steganographic channels are established in data on which error codes are applied. In particular, we experimentally investigate an existing approach of a steganographic channel in a transmission with error correction code with respect to bandwidth作者: 不如屎殼郎 時(shí)間: 2025-3-28 18:18
Yanan Sun,Gary G. Yen,Mengjie Zhangarranged in a rectangular array. Checkbits are determined as parities along rows and columns. In this paper we propose to divide the data bit array into four quadrants ., ., . and .. For every quadrant a parity bit is determined. Compared to a non-modified Cross-Parity Code the number of checkbits i作者: PLAYS 時(shí)間: 2025-3-28 18:57
Yanan Sun,Gary G. Yen,Mengjie Zhangth vector engines. And connected to a Network-on-Chip (NoC) following the Coherent Hub Interface (CHI) protocol. The study quantifies the benefits of vectorization, prefetching, and multichannel NoC configurations using a benchmark for generating memory patterns and indexed accesses. The outcomes pr作者: 苦笑 時(shí)間: 2025-3-28 23:39 作者: Agronomy 時(shí)間: 2025-3-29 03:28
Mitsuo Gen,Runwei Cheng,Shmuel S. Orenture employed by Apple’s x86 emulator, Rosetta 2. The presence of both memory ordering models on the same hardware enables us to thoroughly benchmark and compare their performance characteristics and worst-case workloads..In this paper, we assess the performance implications of TSO on the Apple M1 p作者: 補(bǔ)角 時(shí)間: 2025-3-29 11:17 作者: Physiatrist 時(shí)間: 2025-3-29 13:28 作者: 輕彈 時(shí)間: 2025-3-29 16:39
Evolutionary Design and Manufacture large amount of knowledge on the targeted hardware, available sensors, is required, thus limiting the reusability and adaptability of an already composed ADNA. Recently, the . (.) has been proposed as a countermeasure to this problem. In an ., sensor elements are replaced by so-called . describing 作者: Unsaturated-Fat 時(shí)間: 2025-3-29 21:05
Energy Efficient LSTM Accelerators for?Embedded FPGAs Through Parameterised Architecture Design embedded devices. In this paper, we propose a new hardware accelerator design for LSTMs specially optimised for resource-scarce embedded Field Programmable Gate Arrays (FPGAs). Our design improves the execution speed and reduces energy consumption compared to related work. Moreover, it can be adapt
