標(biāo)題: Titlebook: Analog-Digital Converters for Industrial Applications Including an Introduction to Digital-Analog Co; Frank Ohnh?user Book 2015 Springer-V [打印本頁] 作者: 多愁善感 時(shí)間: 2025-3-21 19:23
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作者: 銀版照相 時(shí)間: 2025-3-21 23:27 作者: Figate 時(shí)間: 2025-3-22 00:40
DIGE-Based Phosphoproteomic Analysis SAR ADCs (Chaps. . and .) and delta-sigma ADCs are most commonly used. This chapter will therefore concentrate on the basics of delta-sigma converters and then on the discrete-time approach utilizing the switched-capacitor technique, which is most commonly used. The alternative continuous-time arch作者: 賠償 時(shí)間: 2025-3-22 07:32 作者: Limerick 時(shí)間: 2025-3-22 11:58 作者: ARENA 時(shí)間: 2025-3-22 15:32 作者: mortuary 時(shí)間: 2025-3-22 17:44 作者: 恭維 時(shí)間: 2025-3-23 01:06
DIGE-Based Phosphoproteomic Analysis SAR ADCs (Chaps. . and .) and delta-sigma ADCs are most commonly used. This chapter will therefore concentrate on the basics of delta-sigma converters and then on the discrete-time approach utilizing the switched-capacitor technique, which is most commonly used. The alternative continuous-time architecture will be discussed in Chap. ..作者: 憤怒事實(shí) 時(shí)間: 2025-3-23 03:24 作者: Paleontology 時(shí)間: 2025-3-23 07:44 作者: ADORN 時(shí)間: 2025-3-23 10:20 作者: 壓艙物 時(shí)間: 2025-3-23 17:41 作者: Amylase 時(shí)間: 2025-3-23 20:19
Frank Ohnh?userDetailed explanations on the development of analog-to-digital converters.Introduction to test methods and quality control in mass production.Advantages and disadvantages of the various architectures.I作者: 發(fā)酵劑 時(shí)間: 2025-3-23 23:03 作者: Amnesty 時(shí)間: 2025-3-24 04:20 作者: 定點(diǎn) 時(shí)間: 2025-3-24 09:39
Basics on Delta-Sigma Converters, SAR ADCs (Chaps. . and .) and delta-sigma ADCs are most commonly used. This chapter will therefore concentrate on the basics of delta-sigma converters and then on the discrete-time approach utilizing the switched-capacitor technique, which is most commonly used. The alternative continuous-time architecture will be discussed in Chap. ..作者: allude 時(shí)間: 2025-3-24 14:22 作者: 我不死扛 時(shí)間: 2025-3-24 18:55 作者: guzzle 時(shí)間: 2025-3-24 21:26 作者: LAIR 時(shí)間: 2025-3-25 03:14 作者: languor 時(shí)間: 2025-3-25 06:11
External Driver Circuitry and Test of ADCs,ation (see Chap. .), if the external connections are adequate [.]. Whenever the ADCs performance is pushed into new dimensions, then the external driver circuitry needs to be reconsidered. The analog inputs and the reference inputs are most critical, because a fast and accurate settling is required 作者: 巫婆 時(shí)間: 2025-3-25 09:05
Digital-to-Analog Converters,. Chapter . discusses the test and verification of ADCs as well as the external circuitry around the ADC in an application. This chapter will now complement the topic of data converters with an introduction of digital-to-analog converters (DACs). In industrial applications, they are often used as th作者: tendinitis 時(shí)間: 2025-3-25 14:10
e the problem of achieving high performance and resolution with the lowest possible power dissipation, while the digital circuitry generates distortion in supply, ground and substrate. This book explains the co978-3-662-51412-2978-3-662-47020-6作者: 公理 時(shí)間: 2025-3-25 16:57
Analog-Digital Converters for Industrial Applications Including an Introduction to Digital-Analog Co作者: Coma704 時(shí)間: 2025-3-25 21:20 作者: 大暴雨 時(shí)間: 2025-3-26 03:43 作者: 聯(lián)想 時(shí)間: 2025-3-26 07:02
DIGE Analysis of Animal Tissuesging the clock frequency. Furthermore, the clock jitter only affects the system noise hardly. The input signal will be sampled at a wrong point of time. However, due to the oversampling, the input frequencies are low anyhow, where noise based on clock jitter can normally be neglected.作者: Atmosphere 時(shí)間: 2025-3-26 09:27
https://doi.org/10.1007/978-1-4939-7268-5e controlling element. The system performance will then fully rely on the DAC and the absolute values such as INL, offset or gain are important. If they are used inside a control loop, which will increment or decrement the DAC value, then equal step size is required, which is reflected in the DNL.作者: Feigned 時(shí)間: 2025-3-26 15:17 作者: cluster 時(shí)間: 2025-3-26 18:43
https://doi.org/10.1007/978-1-0716-2831-7 described in Sect. ..?In a next step, trim solutions for these ADCs were evaluated. A purely digital trim solution is proposed in Sect. . followed by an INL-trim method in Sect. .. A novel method to measure capacitive matching, which is required for the trim algorithm, will further reduce the production costs. It is discussed in Sect. ..作者: 寵愛 時(shí)間: 2025-3-26 21:03
DIGE Analysis of Clinical Specimense external circuitry is also required for a proper test solution. The principles of the different test methods are explained in Sect. .. The performance needs to be optimized for noise and repeatability. The performance of the production test has to be guaranteed and monitored. A quality flow is therefore described in Sect. ..作者: 反感 時(shí)間: 2025-3-27 01:28
Advanced SAR ADC Design, described in Sect. ..?In a next step, trim solutions for these ADCs were evaluated. A purely digital trim solution is proposed in Sect. . followed by an INL-trim method in Sect. .. A novel method to measure capacitive matching, which is required for the trim algorithm, will further reduce the production costs. It is discussed in Sect. ..作者: dragon 時(shí)間: 2025-3-27 06:06 作者: GEAR 時(shí)間: 2025-3-27 10:59
Continuous-Time Delta-Sigma ADCs,ging the clock frequency. Furthermore, the clock jitter only affects the system noise hardly. The input signal will be sampled at a wrong point of time. However, due to the oversampling, the input frequencies are low anyhow, where noise based on clock jitter can normally be neglected.作者: Expiration 時(shí)間: 2025-3-27 15:51
Digital-to-Analog Converters,e controlling element. The system performance will then fully rely on the DAC and the absolute values such as INL, offset or gain are important. If they are used inside a control loop, which will increment or decrement the DAC value, then equal step size is required, which is reflected in the DNL.作者: incarcerate 時(shí)間: 2025-3-27 18:40 作者: BLA 時(shí)間: 2025-3-27 22:44
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