標題: Titlebook: Advances in VLSI and Embedded Systems; Select Proceedings o Zuber Patel,Shilpi Gupta,Nithin Kumar Y. B. Conference proceedings 2021 Springe [打印本頁] 作者: BID 時間: 2025-3-21 19:46
書目名稱Advances in VLSI and Embedded Systems影響因子(影響力)
書目名稱Advances in VLSI and Embedded Systems影響因子(影響力)學科排名
書目名稱Advances in VLSI and Embedded Systems網(wǎng)絡(luò)公開度
書目名稱Advances in VLSI and Embedded Systems網(wǎng)絡(luò)公開度學科排名
書目名稱Advances in VLSI and Embedded Systems被引頻次
書目名稱Advances in VLSI and Embedded Systems被引頻次學科排名
書目名稱Advances in VLSI and Embedded Systems年度引用
書目名稱Advances in VLSI and Embedded Systems年度引用學科排名
書目名稱Advances in VLSI and Embedded Systems讀者反饋
書目名稱Advances in VLSI and Embedded Systems讀者反饋學科排名
作者: 胰島素 時間: 2025-3-21 22:34 作者: 預知 時間: 2025-3-22 01:26
Analysis of Memory-Based Real Fast Fourier Transform Architectures for Low-Area Applications,ed different Memory-based Real Fast Fourier Transform (RFFT) Architectures for low-area applications with the Processing Elements (PE) like High Radix Small Butterfly (HRSB), Urdhva Tiryakbhayam Butterfly (UTB) and a PE with vedic multiplier-carry lookahead units are utilized to reduce the Area, Del作者: Eulogy 時間: 2025-3-22 07:12 作者: 異端 時間: 2025-3-22 11:24 作者: 獎牌 時間: 2025-3-22 12:57
Qualitative and Quantitative Analysis of Parallel-Prefix Adders,erformance of the design. Parallel-Prefix Adders are preferred over conventional adders for higher wordlengths. In this paper, a comprehensive, qualitative and quantitative analysis of popular Parallel-Prefix Adders for various wordlengths (N = 4, 8, 16 and 32) is presented. The adders are implement作者: Ataxia 時間: 2025-3-22 17:19
A Novel Method of Multiplication with Ekanyunena Purvena,t method is applied for BCD(Binary Coded Decial) as well as binary number system. A 4?×?4, 8?×?8 and 16?×?16 bit multiplier is designed using this method and architecture is developed for BCD as well as binary number systems. The performance of this method is compared for area delay and power with a作者: 使成整體 時間: 2025-3-22 23:22 作者: 奇思怪想 時間: 2025-3-23 05:17 作者: AGATE 時間: 2025-3-23 08:01 作者: expunge 時間: 2025-3-23 11:29
Test Time Reduction Using Power-Aware Dynamic Clock Allocation to Scan Vectors,ctive technique to reduce the test time of a system-on-chip (SoC) in the given power budget. As the frequency is relative to the power and the test time, by controlling the test clock frequency, the power consumption and the test time per core can be adjusted to yield an optimal solution to the test作者: 極小量 時間: 2025-3-23 14:12 作者: Audiometry 時間: 2025-3-23 20:41 作者: 幼稚 時間: 2025-3-23 22:56 作者: 雕鏤 時間: 2025-3-24 04:18
Low Power Radix-8 Modulo , Multiplier Using Modified Weighted Method,, while the other two sets use only n bits. In this paper, we present a new algorithm to design radix-8 modulo . multiplier using a modified weighted method with light bias. The multiplier uses only . modulo reduced partial product along with bias term. The new multiplier is also capable to handle z作者: 一再困擾 時間: 2025-3-24 08:07 作者: 缺陷 時間: 2025-3-24 11:02
Image Communication Using Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) Code, signal-to-noise ratio?(SNR). Encoding of the image is done using the Gauss–Jordan elimination method while decoding is done using the min-sum iterative message-passing algorithm using the code length 1152. Hardware design of decoder is based on fully parallel architecture for achieving more through作者: 脫離 時間: 2025-3-24 15:51
Smart Soldier Health Monitoring System Incorporating Embedded Electronics,all the soldiers on the battlefield. A wireless body area network (WBAN) is created by treating each soldier as a node and each node consists of different sensors monitoring the condition of that particular soldier which could be integrated inside a uniform or a bulletproof jacket. The attributes tr作者: critique 時間: 2025-3-24 21:57 作者: 故意釣到白楊 時間: 2025-3-24 23:09
https://doi.org/10.1007/978-3-540-85634-4 of digital verification are constraint random stimulus generation, functional coverage, and self-checking test benches that make digital verification very robust. However, analog verification is still a manual process. Therefore, the demand is to transform analog verification techniques into an aut作者: 匍匐 時間: 2025-3-25 06:55 作者: 令人發(fā)膩 時間: 2025-3-25 10:21
Nonconvex Optimization and Its Applicationsed different Memory-based Real Fast Fourier Transform (RFFT) Architectures for low-area applications with the Processing Elements (PE) like High Radix Small Butterfly (HRSB), Urdhva Tiryakbhayam Butterfly (UTB) and a PE with vedic multiplier-carry lookahead units are utilized to reduce the Area, Del作者: NOTCH 時間: 2025-3-25 15:18 作者: Cholesterol 時間: 2025-3-25 16:58
Limited Memory Quasi-Newton Algorithms,f things. Intelligent transportation system works on major application area for development of smart cities in current scenario. One of the ITS application i.e. vehicle detection and analysis of moving vehicle in the accident notification system was implemented using Arduino Mega 2560 microcontrolle作者: TERRA 時間: 2025-3-25 23:16
Nonconvex Optimization and Its Applicationserformance of the design. Parallel-Prefix Adders are preferred over conventional adders for higher wordlengths. In this paper, a comprehensive, qualitative and quantitative analysis of popular Parallel-Prefix Adders for various wordlengths (N = 4, 8, 16 and 32) is presented. The adders are implement作者: 秘密會議 時間: 2025-3-26 01:34 作者: Accord 時間: 2025-3-26 04:25 作者: 蛤肉 時間: 2025-3-26 11:46 作者: Albinism 時間: 2025-3-26 16:36 作者: 單調(diào)性 時間: 2025-3-26 20:15 作者: Synovial-Fluid 時間: 2025-3-27 00:33 作者: Haphazard 時間: 2025-3-27 04:46 作者: 天然熱噴泉 時間: 2025-3-27 08:28
7 Carbon centered high-spin polyradicals,the timing performance with minimum area overhead. To improve its performance, a splitting structure of the adder circuit rather than a single adder is used in linear congruential generator (LCG). Its effect on the design of a dual-CLCG is observed to compute some of the essential performance parame作者: Cpr951 時間: 2025-3-27 12:35 作者: 濃縮 時間: 2025-3-27 15:27 作者: Memorial 時間: 2025-3-27 21:42 作者: 尾隨 時間: 2025-3-27 23:08 作者: 全部逛商店 時間: 2025-3-28 05:50
7 Carbon centered high-spin polyradicals,roposed Power Amplifier (PA) design exhibits the simplest topology to fulfill the requirement of low gain ripple, good linearity, and small group delay variations all simultaneously for Ultra-Wide-Band (UWB) application and covering only 0.75 mm. area of silicon. In order to obtain low gain ripple, 作者: Precursor 時間: 2025-3-28 07:30
Image Communication Using Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) Code, signal-to-noise ratio?(SNR). Encoding of the image is done using the Gauss–Jordan elimination method while decoding is done using the min-sum iterative message-passing algorithm using the code length 1152. Hardware design of decoder is based on fully parallel architecture for achieving more throughput.作者: micronized 時間: 2025-3-28 14:30
https://doi.org/10.1007/978-981-15-6229-7CAD for VLSI; Devices and Emerging Technologies; Embedded Design; Testing and Verification; VLSI Design; 作者: restrain 時間: 2025-3-28 17:57 作者: employor 時間: 2025-3-28 20:28 作者: acolyte 時間: 2025-3-29 02:39 作者: 偏見 時間: 2025-3-29 03:29 作者: macular-edema 時間: 2025-3-29 11:10
Lecture Notes in Electrical Engineeringhttp://image.papertrans.cn/a/image/150085.jpg作者: emulsify 時間: 2025-3-29 15:06 作者: Debark 時間: 2025-3-29 19:02
Nonconvex Optimization and Its Applicationsnstitute the Frickse-Morse model of 2R-1C network. Arduino Uno controls digital potentiometer via Serial Peripheral Interface (SPI), LCD via Inter Integrated Circuit (I2C) and multiplexer via digital pins D7-D0. The implemented bio-impedance simulator is validated by using as a varying load of a pre作者: 的染料 時間: 2025-3-29 22:26 作者: ILEUM 時間: 2025-3-30 01:01
Automated Simulator for the Validation of Bio-Impedance Devices,nstitute the Frickse-Morse model of 2R-1C network. Arduino Uno controls digital potentiometer via Serial Peripheral Interface (SPI), LCD via Inter Integrated Circuit (I2C) and multiplexer via digital pins D7-D0. The implemented bio-impedance simulator is validated by using as a varying load of a pre作者: 情感脆弱 時間: 2025-3-30 05:29
Optimization of MEMS-Based Capacitive Sensor with High-k Dielectric for Detection of Heavy Metal Iothis fF range of capacitance. An individual capacitance to digital converter (CDC) circuit is required to measure this capacitance produced by MEMS-based sensors. Hence, we have used the HfO. as High-k dielectric layer to increase the sensor capacitance in picofarads (pF) range to use the market ava作者: 削減 時間: 2025-3-30 10:08 作者: 虛假 時間: 2025-3-30 13:04
Qualitative and Quantitative Analysis of Parallel-Prefix Adders,tion. Results indicate that Kogge–Stone adder is the fastest adder with . = 104.93 MHz but is most area-power inefficient consuming 133 LUTs and 23.756?W power at 10 GHz. Sklansky adder is most power efficient consuming 22.857?W power at 10 GHz. Brent–Kung adder is area optimum consuming 62 LUTs.作者: Perceive 時間: 2025-3-30 19:07
A Novel Method of Multiplication with Ekanyunena Purvena,s power dissipation is calculated using XPower analyzer. The performance of proposed multiplier is compared with conventional array multiplier.The simulation results demonstrates the improvement in processing speed as well as power consumption.作者: capillaries 時間: 2025-3-31 00:01 作者: 懲罰 時間: 2025-3-31 03:08 作者: Abominate 時間: 2025-3-31 07:56
,Impact of Multi-Metal Gate Stacks on the Performance of β,Ga,O, MOS Structure,lti-metal gate stack arrangements on the performance of β.Ga.O. MOS Structure. The performance parameters used in the analysis are I., I., I./I. g. and g.. It is observed that the Ti/Au metal stack arrangement shows better results among all the metal stack arrangements and hence found to be suitable for high power RF applications with low losses.作者: SHRIK 時間: 2025-3-31 10:58
Need for Predictive Data Analytics in Cold Chain Management,ld chain. In this work, predictive data analytics is proposed to make real-time predictions about time–temperature relationship considering various internal and external factors to avoid temperature abuse during transportation and thus predict the quality of food.作者: theta-waves 時間: 2025-3-31 16:02
FPGA-Based Implementation of Artifact Suppression and Feature Extraction,mplantable Application-Specific Integrated Circuit (ASIC) development. Focus of this paper is to maintain the trade-off between adequate accuracy and low complexity. FPGA implementation demonstrates feature extraction using Haar wavelet transform gives better trade-off between accuracy and complexity of the hardware.作者: Defense 時間: 2025-3-31 20:34 作者: 膽小鬼 時間: 2025-4-1 00:18
Design of Prominent Single-Precision 32-Bit Floating-Point Adder Using Single-Electron Transistor Oder. SET-based FP adder consumes very less power and also very less delay. For simulation and verification, CADENCE virtuoso is used. According to our results, SET-based FP addition has 79.70% improvement in power and 97.67% faster than CMOS-based FP.作者: liposuction 時間: 2025-4-1 03:52 作者: 完全 時間: 2025-4-1 09:29 作者: milligram 時間: 2025-4-1 11:10
Nonconvex Optimization and Its Applicationsadix algorithms. The architectures are implemented on various Xilinx Field Programmable Gate Array (FPGA) devices and also on 180?nm Application-Specific Integrated Circuit (ASIC) to compare different parameters like Area, Delay and Power.作者: 缺乏 時間: 2025-4-1 15:09 作者: 箴言 時間: 2025-4-1 20:49
