標(biāo)題: Titlebook: Advances in VLSI and Embedded Systems; Select Proceedings o Anand D. Darji,Deepak Joshi,Ray Sheriff Conference proceedings 2023 The Editor( [打印本頁(yè)] 作者: minuscule 時(shí)間: 2025-3-21 17:42
書(shū)目名稱(chēng)Advances in VLSI and Embedded Systems影響因子(影響力)
書(shū)目名稱(chēng)Advances in VLSI and Embedded Systems影響因子(影響力)學(xué)科排名
書(shū)目名稱(chēng)Advances in VLSI and Embedded Systems網(wǎng)絡(luò)公開(kāi)度
書(shū)目名稱(chēng)Advances in VLSI and Embedded Systems網(wǎng)絡(luò)公開(kāi)度學(xué)科排名
書(shū)目名稱(chēng)Advances in VLSI and Embedded Systems被引頻次
書(shū)目名稱(chēng)Advances in VLSI and Embedded Systems被引頻次學(xué)科排名
書(shū)目名稱(chēng)Advances in VLSI and Embedded Systems年度引用
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書(shū)目名稱(chēng)Advances in VLSI and Embedded Systems讀者反饋
書(shū)目名稱(chēng)Advances in VLSI and Embedded Systems讀者反饋學(xué)科排名
作者: finale 時(shí)間: 2025-3-21 20:16
A Feed-Forward Gain Enhancement Technique in a Narrow-Band Low Noise Amplifier Using Active Inductoe FFP enhances the gain by 12.2% and reduces the NF by 7.2% compared to the modified cascode LNA. The figure-of-merit shows that the designed amplifier is around two times better than the previously reported ones.作者: Substance-Abuse 時(shí)間: 2025-3-22 03:50
Design and Implementation of Fault Tolerance and Diagnosis Technique for Arithmetic Logic Unit (ALU STARTER EDITION 10.1d Revision: 2012.11. Simulation has been done under all possible fault cases for the considered module and as a result, the system will be able to go into a fail-safe and diagnosis state as per the proposed technique. It is capable of identifying faulty modules in case of extern作者: 脆弱么 時(shí)間: 2025-3-22 08:22
,Pneumatic Calibrator for?Heterodyne Interferometer,or in the laboratory. Calibration has been done using single and multiple path length displacements. The displacement variation is recorded using an ultrasonic sensor (HC-SR04). The developed calibrator has 2–10 cm distance range with 0.3?cm range accuracy. The developed calibrator will be used in d作者: 投射 時(shí)間: 2025-3-22 12:03
Real-Time Object Detection and Recognition for the Visually Impaired: A YOLOv3 Approach,m the entire image in just one evaluation. Since the entire pipeline is just one network, optimization can be done easily on the detection performance. The YOLO model has various versions like YOLOv2, YOLOv3, YOLOv4 and YOLO9000. It outperforms other detection methods when generalizing natural image作者: addict 時(shí)間: 2025-3-22 15:42 作者: arsenal 時(shí)間: 2025-3-22 17:54 作者: Saline 時(shí)間: 2025-3-23 01:12
Assessing Effect of Variability in Nano-Scale Futuristic On-Chip Interconnects,cess-induced variations using SPICE at 32?nm technology node. Furthermore, the effective time-domain analysis tool, eye diagram is investigated for the stated interconnect system model. Eye diagram is implemented on Advanced Design System (ADS) tool for the estimation of digital signal errors in tim作者: 熱情的我 時(shí)間: 2025-3-23 04:47
A Heuristic Algorithm for Module Placement in Digital Microfluidic Biochips,es should be placed according to the schedule inputted with minimum deviation and use as little area as possible to facilitate fault-tolerance. Two popular bioassays, multiplexed in vitro diagnostics and Colorimetric protein assay, are used for experimental evaluation.作者: buoyant 時(shí)間: 2025-3-23 07:26
Conjugate Direction Methods in Optimizationusly reported linearization techniques that improve both IIP2 and IIP3 are investigated thoroughly and divided into five main categories: (a) feedback, (b) feedforward, (c) complementary derivative superposition (CDS), (d) noise/distortion cancellation, and e) post distortion. After extensive analys作者: NAIVE 時(shí)間: 2025-3-23 13:02 作者: insipid 時(shí)間: 2025-3-23 16:34
https://doi.org/10.1007/978-3-642-18560-1 STARTER EDITION 10.1d Revision: 2012.11. Simulation has been done under all possible fault cases for the considered module and as a result, the system will be able to go into a fail-safe and diagnosis state as per the proposed technique. It is capable of identifying faulty modules in case of extern作者: sacrum 時(shí)間: 2025-3-23 21:38
Acute Versus Nonobtuse Tetrahedralizationsor in the laboratory. Calibration has been done using single and multiple path length displacements. The displacement variation is recorded using an ultrasonic sensor (HC-SR04). The developed calibrator has 2–10 cm distance range with 0.3?cm range accuracy. The developed calibrator will be used in d作者: SNEER 時(shí)間: 2025-3-24 01:41 作者: Aura231 時(shí)間: 2025-3-24 04:16 作者: nascent 時(shí)間: 2025-3-24 06:36 作者: analogous 時(shí)間: 2025-3-24 11:05 作者: dithiolethione 時(shí)間: 2025-3-24 18:35
Limited Memory Quasi-Newton Algorithms,es should be placed according to the schedule inputted with minimum deviation and use as little area as possible to facilitate fault-tolerance. Two popular bioassays, multiplexed in vitro diagnostics and Colorimetric protein assay, are used for experimental evaluation.作者: 無(wú)聊點(diǎn)好 時(shí)間: 2025-3-24 19:36 作者: DUST 時(shí)間: 2025-3-25 03:03 作者: WITH 時(shí)間: 2025-3-25 06:15
Advances in VLSI and Embedded Systems978-981-19-6780-1Series ISSN 1876-1100 Series E-ISSN 1876-1119 作者: custody 時(shí)間: 2025-3-25 07:59 作者: 收集 時(shí)間: 2025-3-25 11:59 作者: hemoglobin 時(shí)間: 2025-3-25 16:57
Anand D. Darji,Deepak Joshi,Ray SheriffIncludes outstanding research papers presented at AVES 2021.Discusses new findings in VLSI and embedded systems.Serves as a reference resource for researchers and practitioners in academia and industr作者: 貨物 時(shí)間: 2025-3-25 23:14 作者: 音的強(qiáng)弱 時(shí)間: 2025-3-26 01:05
Queer Propositions: Sex and Sexualities,e major components used in designing PLL. This paper presents a novel PD and PFD circuit designed using dynamic CMOS architecture. A thorough step by step examination of PD and PFD design is carried out in this work. The proposed circuit optimizes the channel length, aspect ratio and supply voltage 作者: 小隔間 時(shí)間: 2025-3-26 07:21 作者: gusher 時(shí)間: 2025-3-26 09:18 作者: commune 時(shí)間: 2025-3-26 14:03
Conjugate Direction Methods in Optimizationd 8T SRAM by connecting word line and one nMOS with high width in the bottom of the twisted connected inverter pair. This work illustrates a 9T SRAM cell that dissipates low power and has high speed during read time and write time. This SRAM cell is a little modification of the SE8T SRAM cell, in wh作者: 泥瓦匠 時(shí)間: 2025-3-26 17:05 作者: SPER 時(shí)間: 2025-3-26 21:06
The numerical experiment: preliminaries,proximate compressor. The proposed approach reduces the switching activity, thereby reduces the dynamic power. The proposed compressor is 78.33% energy efficient than the existing ones. The proposed approximate multiplier is used in image processing application to demonstrate the output visual quali作者: 爭(zhēng)吵加 時(shí)間: 2025-3-27 03:04
Conjugate Duality in Convex Optimizationimage and multimedia processing, data mining, etc. due to their inherent error tolerance. Multipliers are the most prominent circuits which are required for deploying these applications on digital processors. In this paper, a power-efficient unsigned multiplier is designed that uses a novel approxim作者: Paleontology 時(shí)間: 2025-3-27 07:27
https://doi.org/10.1007/978-3-642-04900-2all die area. The proposed design consists of two stages. The first part comprises a modified cascode stage containing dual common source transistors. The authors replaced the passive drain inductor with an active inductor to make the circuit area-efficient. The second part consists of a feed-forwar作者: Coma704 時(shí)間: 2025-3-27 12:19 作者: 取消 時(shí)間: 2025-3-27 15:35
https://doi.org/10.1007/978-3-642-18560-1re the most important and core component of the processor. In the application where the system is under harsh environmental conditions, it is most important to design a fault-tolerant and reliable processor for the proper continuity of operation on the field. We have demonstrated the combined techni作者: 政府 時(shí)間: 2025-3-27 18:13 作者: DEMUR 時(shí)間: 2025-3-28 00:36 作者: Halfhearted 時(shí)間: 2025-3-28 05:02
Robert Horváth,István Faragó,Willy Schilderss the dependency on the agriculture industry. But in today’s scenario because of low yield, less rainfall, etc., a dearth of manpower is created in this agricultural sector and people are moving to live in the cities, and villages are becoming more and more urbanized. On the other hand, the field of作者: Robust 時(shí)間: 2025-3-28 07:19
https://doi.org/10.1007/978-3-540-85634-4for an effective and long-term vaccine. In the present scenario, people are relying on wearing mask, self-quarantine, social-distancing and sanitizing hands for defending this infectious coronavirus. The health-care units, academicians, researchers and governments as well as business houses are tryi作者: Accomplish 時(shí)間: 2025-3-28 13:47
Memoryless Quasi-Newton Methods,) digital signals or Non-Return-to-Zero (NRZ), Manchester, differential Manchester and Bipolar data bits. This study is done using simulations run on Sentaurus (sdevice) TCAD with a resistive load Silicon Double Gate TFET inverter, with an output load capacitance . of 3 fF, 50 nm channel length (.) 作者: gerrymander 時(shí)間: 2025-3-28 16:46 作者: paradigm 時(shí)間: 2025-3-28 21:47
Memoryless Quasi-Newton Methods,ion technique has been to detect the biomolecules. Drain current sensitivity (ΔI.) and threshold voltage sensitivity (ΔV.) are taken as sensitivity metrics for biomolecule detection. It is observed that JL-DG-MOSFET gives a very good ΔI. in the order of 10.. Further, the impact of channel parameters作者: 壓碎 時(shí)間: 2025-3-28 23:01
Limited Memory Quasi-Newton Algorithms,m CMOS-based LDO regulator. The LDO regulator is implemented using an Error amplifier (EA) which is a TFET-based two-stage Op-Amp. The EA has a high open-loop DC gain of 66.8 dB and phase margin (PM) of 60.9.. The Gain Bandwidth Product (GBW) of the EA is 1.44 GHz, 3 dB frequency of 708.12 kHz, and 作者: obsolete 時(shí)間: 2025-3-29 06:13 作者: 險(xiǎn)代理人 時(shí)間: 2025-3-29 08:22
Conference proceedings 2023ok covers cutting-edge original research in VLSI design, devices and emerging technologies, embedded systems, and CAD for VLSI. To address the demand for complex and high-functionality systems as well as portable consumer electronics, the contents focus on advanced topics of circuit and systems desi作者: 記憶法 時(shí)間: 2025-3-29 11:44
Analysis and Modification of Low Power and High Speed 9T SRAM Cell,ich one of the ends of the cell is used to write the information and the other is used to read the information written on the cell. In the same cell, one nMOS transistor has been added to provide better read access time. This stacking of the transistor provides the cell a better path to discharge the bit lines.作者: 機(jī)密 時(shí)間: 2025-3-29 15:40
,Approximate Computing-Based Unsigned Multipliers for?Image Processing Applications,ate 4–2 compressor. Simulation results demonstrate that the proposed multipliers have 11.07. reduction in energy compared to exact multiplier and provide a high PSNR in the range of 20.47 to 35.23 dB for image multiplication application.作者: ablate 時(shí)間: 2025-3-29 23:40
Memoryless Quasi-Newton Methods,ing of L. improves the threshold voltage sensitivity. However, we observed a peak at L.?=?150?nm for drain current sensitivity. Hence, a lower T. (= 8?nm) and L. (= 150?nm) results in better sensitivities and thus can be used for designing JL-DG-FET based biosensors.作者: 露天歷史劇 時(shí)間: 2025-3-30 00:17 作者: fetter 時(shí)間: 2025-3-30 07:49
Conjugate Direction Methods in Optimizationich one of the ends of the cell is used to write the information and the other is used to read the information written on the cell. In the same cell, one nMOS transistor has been added to provide better read access time. This stacking of the transistor provides the cell a better path to discharge the bit lines.作者: angiography 時(shí)間: 2025-3-30 10:11 作者: flamboyant 時(shí)間: 2025-3-30 15:10 作者: 占卜者 時(shí)間: 2025-3-30 20:14 作者: heartburn 時(shí)間: 2025-3-30 20:54
https://doi.org/10.1057/9781137480910sults, the proposed modular reduction unit is improved in terms of total cell count and dynamic power consumption by (56% and 46%) over the conventional and modified conventional methods. Power Delay Product and Energy delay Product of the proposed MRU is enhanced by (~56%,?~?44%) over the conventional and modified conventional methods.作者: 修正案 時(shí)間: 2025-3-31 04:04
Obtaining an initial estimate , of ,10?T SRAM cell has the least variation in static performance. Another parameter used to compare the performance of the cells is leakage current. This identifies 9?T SRAM bit cell has the maximum leakage current with 635 pA and 630 pA for Q?=?‘0’ and ‘1’ respectively.作者: magnanimity 時(shí)間: 2025-3-31 08:53 作者: Senescent 時(shí)間: 2025-3-31 12:24
Limited Memory Quasi-Newton Algorithms,r . variation from 0 to 50 mA. The designed LDO voltage regulator working with a reference voltage of 0.72 V offers a PSRR 39.6 dB for frequency up to 210 kHz. The designed TFET-based LDO voltage regulator consumes 113.86 .W of power.作者: 火光在搖曳 時(shí)間: 2025-3-31 16:49
Modeling and Analysis of Low Power High-Speed Phase Detector and Phase Frequency Detector Using Nan4?V. Aspect ratio (width to length ratios) is varied in the range of 1–5. Tanner T-Spice tool is used for simulation. Compared with the several techniques proposed before, the presented circuit gives the best tradeoff to choose between different channel lengths according to user requirements.作者: GORGE 時(shí)間: 2025-3-31 17:48 作者: 不成比例 時(shí)間: 2025-4-1 00:01 作者: colostrum 時(shí)間: 2025-4-1 03:34
,Design and?Implementation of?IoT-Based System for?Tracking and?Monitoring of?Suspected COVID-19 Patt can be used to reduce the chances of community transmission of this deadly virus. Proposed reusable cost-effective system can help the hospital and local authority to monitor and track the movement of quarantined people.作者: 走路左晃右晃 時(shí)間: 2025-4-1 09:09
Design of a TFET-Based Temperature Invariant LDO Voltage Regulator,r . variation from 0 to 50 mA. The designed LDO voltage regulator working with a reference voltage of 0.72 V offers a PSRR 39.6 dB for frequency up to 210 kHz. The designed TFET-based LDO voltage regulator consumes 113.86 .W of power.作者: 溺愛(ài) 時(shí)間: 2025-4-1 13:25
1876-1100 ce for researchers and practitioners in academia and industr.This book presents select peer-reviewed proceedings of the 2nd International Conference on Advances in VLSI and Embedded Systems (AVES 2021). This book covers cutting-edge original research in VLSI design, devices and emerging technologies作者: 強(qiáng)制令 時(shí)間: 2025-4-1 18:09
Ladislav Luk?an,Ctirad Matonoha,Jan Vl?ekfactor applications. The proposed scheme has been designed and simulated using a 0.18 .m CMOS technology node for an operating frequency of 953?MHz. A study of the . characteristics exhibits a magnitude of greater than ?20 dB, thereby illustrating the effectiveness of the proposed matching scheme.作者: 有危險(xiǎn) 時(shí)間: 2025-4-1 21:55
,A Fully On-Chip Tunable Impedance Matching Strategy for?Maximum Power Transfer in?RF Energy Harvestfactor applications. The proposed scheme has been designed and simulated using a 0.18 .m CMOS technology node for an operating frequency of 953?MHz. A study of the . characteristics exhibits a magnitude of greater than ?20 dB, thereby illustrating the effectiveness of the proposed matching scheme.
